From: Stanley Chu <yschu@nuvoton.com>

The Nuvoton NPCM845 I3C controller has a hardware quirk
(SVC_I3C_QUIRK_FALSE_SLVSTART) where a spurious SLVSTART interrupt
may be generated. This series addresses two separate issues related to
this quirk:

1. A race condition where a real IBI arrives after MSTATUS is latched
   but before the SLVSTART status is cleared, causing the IRQ handler
   to return early on a stale snapshot and miss the pending IBI. Fixed
   by re-reading MSTATUS after clearing the interrupt status.

2. When a target holds SDA low, the controller reports a Master Request
   (MR). Emitting the required STOP condition in response spuriously
   sets SLVSTART again, re-entering the MR handler in a loop and causing
   an IRQ storm. Fixed by explicitly clearing SLVSTART after the STOP
   in the MR handler.

Stanley Chu (2):
  i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845
  i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

 drivers/i3c/master/svc-i3c-master.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

-- 
2.34.1

On Mon, 13 Apr 2026 08:50:38 +0800, Stanley Chu wrote:
> From: Stanley Chu <yschu@nuvoton.com>
> 
> The Nuvoton NPCM845 I3C controller has a hardware quirk
> (SVC_I3C_QUIRK_FALSE_SLVSTART) where a spurious SLVSTART interrupt
> may be generated. This series addresses two separate issues related to
> this quirk:
> 
> [...]

Applied, thanks!

[1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845
      https://git.kernel.org/i3c/c/fa1d4fa118f4
[2/2] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845
      https://git.kernel.org/i3c/c/1effa3adfe53

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com