.../bindings/display/ti/ti,am65x-dss.yaml | 66 ++++++++++++++----- 1 file changed, 48 insertions(+), 18 deletions(-)
The AM62L DSS [1] support incorrectly used the same register and
clock constraints as AM65x, but AM62L has a single video port
Fix this by adding conditional constraints that properly define the
register regions and clocks for AM62L DSS (single video port) versus
other AM65x variants (dual video port).
[1]: Section 12.7 (Display Subsystem and Peripherals)
Link : https://www.ti.com/lit/pdf/sprujb4
Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS")
Cc: stable@vger.kernel.org
Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
Validated the changes with some examples:
https://gist.github.com/swamiljain/79f30568c9ece89f5a20218f52647486
Changelog:
v2->v3:
- Reduce redundancy and use constraints suggested by maintainers
- Remove blank line between the tags
Link to v2:
https://lore.kernel.org/all/20260129150601.185882-1-s-jain1@ti.com/
v1->v2:
- Remove oneOf from top level constraints, it makes bindings redundant
- Remove minItems from top level constraints
- "dma-coherent" property shouldn't be changed in v1 itself
- Add description for reg-names, clock and clock-names
- Add constraints specific to AM62L and for other SoCs within allOf
check
Link to v1:
https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/
---
.../bindings/display/ti/ti,am65x-dss.yaml | 66 ++++++++++++++-----
1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 38fcee91211e..d8a05bf62c2f 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -36,34 +36,50 @@ properties:
reg:
description:
Addresses to each DSS memory region described in the SoC's TRM.
- items:
- - description: common DSS register area
- - description: VIDL1 light video plane
- - description: VID video plane
- - description: OVR1 overlay manager for vp1
- - description: OVR2 overlay manager for vp2
- - description: VP1 video port 1
- - description: VP2 video port 2
- - description: common1 DSS register area
+ oneOf:
+ - items:
+ - description: common DSS register area
+ - description: VIDL1 light video plane
+ - description: VID video plane
+ - description: OVR1 overlay manager for vp1
+ - description: OVR2 overlay manager for vp2
+ - description: VP1 video port 1
+ - description: VP2 video port 2
+ - description: common1 DSS register area
+ - items:
+ - description: common DSS register area
+ - description: VIDL1 light video plane
+ - description: OVR1 overlay manager for vp1
+ - description: VP1 video port 1
+ - description: common1 DSS register area
reg-names:
- items:
- - const: common
- - const: vidl1
- - const: vid
- - const: ovr1
- - const: ovr2
- - const: vp1
- - const: vp2
- - const: common1
+ oneOf:
+ - items:
+ - const: common
+ - const: vidl1
+ - const: vid
+ - const: ovr1
+ - const: ovr2
+ - const: vp1
+ - const: vp2
+ - const: common1
+ - items:
+ - const: common
+ - const: vidl1
+ - const: ovr1
+ - const: vp1
+ - const: common1
clocks:
+ minItems: 2
items:
- description: fck DSS functional clock
- description: vp1 Video Port 1 pixel clock
- description: vp2 Video Port 2 pixel clock
clock-names:
+ minItems: 2
items:
- const: fck
- const: vp1
@@ -179,6 +195,20 @@ allOf:
ports:
properties:
port@1: false
+ clock-names:
+ maxItems: 2
+ clocks:
+ maxItems: 2
+ reg:
+ maxItems: 5
+ else:
+ properties:
+ clock-names:
+ minItems: 3
+ clocks:
+ minItems: 3
+ reg:
+ minItems: 8
- if:
properties:On Fri, Apr 10, 2026 at 04:29:55PM +0530, Swamil Jain wrote: > clocks: > + minItems: 2 > items: > - description: fck DSS functional clock > - description: vp1 Video Port 1 pixel clock > - description: vp2 Video Port 2 pixel clock > > clock-names: > + minItems: 2 > items: > - const: fck > - const: vp1 > @@ -179,6 +195,20 @@ allOf: > ports: > properties: > port@1: false > + clock-names: > + maxItems: 2 > + clocks: > + maxItems: 2 > + reg: > + maxItems: 5 Also constrain for reg-names, > + else: > + properties: > + clock-names: > + minItems: 3 > + clocks: > + minItems: 3 > + reg: > + minItems: 8 Same here, please. And if you are sending new version: they should be listed in the same order as in top-level properties, so reg, reg-names, clocks and clock-names. (juging by the diff) Best regards, Krzysztof
Hi Krzysztof, On 4/11/26 19:37, Krzysztof Kozlowski wrote: > On Fri, Apr 10, 2026 at 04:29:55PM +0530, Swamil Jain wrote: >> clocks: >> + minItems: 2 >> items: >> - description: fck DSS functional clock >> - description: vp1 Video Port 1 pixel clock >> - description: vp2 Video Port 2 pixel clock >> >> clock-names: >> + minItems: 2 >> items: >> - const: fck >> - const: vp1 >> @@ -179,6 +195,20 @@ allOf: >> ports: >> properties: >> port@1: false >> + clock-names: >> + maxItems: 2 >> + clocks: >> + maxItems: 2 >> + reg: >> + maxItems: 5 > > Also constrain for reg-names, > Sure, will add in v4. >> + else: >> + properties: >> + clock-names: >> + minItems: 3 >> + clocks: >> + minItems: 3 >> + reg: >> + minItems: 8 > > Same here, please. > > And if you are sending new version: they should be listed in the same > order as in top-level properties, so reg, reg-names, clocks and > clock-names. (juging by the diff) Yeah, sure, will keep the order. Thanks for the feedback, will re-spin the patch. Regards, Swamil. > > Best regards, > Krzysztof >
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