Add the device nodes for the multimedia clock controllers (cambistmclkcc,
camcc, videocc, gpucc) for Qualcomm Eliza SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 54 +++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a7a0ac40ce6252a138bed06c7c190ada3ea61a3..7a2a3dba86b9395743781cdf724e81733140ecd0 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -709,6 +709,18 @@ aggre2_noc: interconnect@1700000 {
#interconnect-cells = <2>;
};
+ cambistmclkcc: clock-controller@1760000 {
+ compatible = "qcom,eliza-cambistmclkcc";
+ reg = <0x0 0x01760000 0x0 0x6000>;
+
+ clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&sleep_clk>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
mmss_noc: interconnect@1780000 {
compatible = "qcom,eliza-mmss-noc";
reg = <0x0 0x01780000 0x0 0x7d800>;
@@ -862,6 +874,23 @@ tcsr: clock-controller@1fbf000 {
#reset-cells = <1>;
};
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,eliza-gpucc";
+ reg = <0x0 0x03d90000 0x0 0xa000>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
+
+ power-domains = <&rpmhpd RPMHPD_MX>,
+ <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,eliza-lpass-ag-noc";
reg = <0x0 0x07e40000 0x0 0xe080>;
@@ -883,6 +912,31 @@ lpass_lpicx_noc: interconnect@7420000 {
#interconnect-cells = <2>;
};
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,eliza-videocc";
+ reg = <0x0 0xaaf0000 0x0 0x10000>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&sleep_clk>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,eliza-camcc";
+ reg = <0x0 0x0ade0000 0x0 0x20000>;
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&sleep_clk>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,eliza-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x40000>,
--
2.34.1On Thu, Apr 09, 2026 at 11:40:49PM +0530, Taniya Das wrote: > Add the device nodes for the multimedia clock controllers (cambistmclkcc, > camcc, videocc, gpucc) for Qualcomm Eliza SoC. > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/eliza.dtsi | 54 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) Note that this patch and drivers parches were likely not tested. Please mark patches you wish others to test as RFT. Best regards, Krzysztof
On 4/10/2026 1:14 PM, Krzysztof Kozlowski wrote: > On Thu, Apr 09, 2026 at 11:40:49PM +0530, Taniya Das wrote: >> Add the device nodes for the multimedia clock controllers (cambistmclkcc, >> camcc, videocc, gpucc) for Qualcomm Eliza SoC. >> >> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> >> --- >> arch/arm64/boot/dts/qcom/eliza.dtsi | 54 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 54 insertions(+) > > Note that this patch and drivers parches were likely not tested. > > Please mark patches you wish others to test as RFT. > Krzysztof, please find the logs, if you need the clk_summary I can add those as well. / # dmesg [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd801] [ 0.000000] Linux version 7.0.0-rc7-next-20260408-00008-g476992104d28-dirty () (aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0, GNU ld (GNU Binutils for Ubuntu) 2.38) #19 SMP PREEMPT Thu Apr 9 16:46:11 +0530 2026 [ 0.000000] KASLR enabled [ 0.000000] random: crng init done [ 0.000000] Machine model: Qualcomm Technologies, Inc. Eliza MTP [ 0.000000] printk: debug: ignoring loglevel setting. [ 0.000000] efi: UEFI not found. [ 0.000000] earlycon: qcom_geni0 at MMIO 0x0000000000894000 (options '115200n8') [ 0.000000] printk: legacy bootconsole [qcom_geni0] enabled [ 0.000000] OF: reserved mem: 0x0000000080000000..0x0000000080dfffff (14336 KiB) nomap non-reusable gunyah-hyp@80000000 [ 0.000000] OF: reserved mem: 0x0000000080e00000..0x0000000080e3ffff (256 KiB) nomap non-reusable cpusys-vm-mem@80e00000 [ 0.000000] OF: reserved mem: 0x0000000081200000..0x00000000813fffff (2048 KiB) nomap non-reusable cpucp@81200000 [ 0.000000] OF: reserved mem: 0x0000000081a00000..0x0000000081a3ffff (256 KiB) nomap non-reusable xbl-dtlog@81a00000 [ 0.000000] OF: reserved mem: 0x0000000081c00000..0x0000000081c5ffff (384 KiB) nomap non-reusable aop-image@81c00000 [ 0.000000] OF: reserved mem: 0x0000000081c60000..0x0000000081c7ffff (128 KiB) nomap non-reusable aop-cmd-db@81c60000 [ 0.000000] OF: reserved mem: 0x0000000081c80000..0x0000000081cf3fff (464 KiB) nomap non-reusable aop-tme-uefi-merged@81c80000 -- Thanks, Taniya Das
On 09/04/2026 19:10, Taniya Das wrote:
> + videocc: clock-controller@aaf0000 {
> + compatible = "qcom,eliza-videocc";
> + reg = <0x0 0xaaf0000 0x0 0x10000>;
> +
> + clocks = <&bi_tcxo_div2>,
> + <&sleep_clk>,
> + <&gcc GCC_VIDEO_AHB_CLK>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + camcc: clock-controller@ade0000 {
> + compatible = "qcom,eliza-camcc";
> + reg = <0x0 0x0ade0000 0x0 0x20000>;
> +
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&bi_tcxo_div2>,
> + <&sleep_clk>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
This looks odd.
Why do these two controllers have no power-domains ?
---
bod
On 4/10/2026 12:10 AM, Bryan O'Donoghue wrote:
> On 09/04/2026 19:10, Taniya Das wrote:
>> + videocc: clock-controller@aaf0000 {
>> + compatible = "qcom,eliza-videocc";
>> + reg = <0x0 0xaaf0000 0x0 0x10000>;
>> +
>> + clocks = <&bi_tcxo_div2>,
>> + <&sleep_clk>,
>> + <&gcc GCC_VIDEO_AHB_CLK>;
>> +
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + camcc: clock-controller@ade0000 {
>> + compatible = "qcom,eliza-camcc";
>> + reg = <0x0 0x0ade0000 0x0 0x20000>;
>> +
>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
>> + <&bi_tcxo_div2>,
>> + <&sleep_clk>;
>> +
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>
> This looks odd.
>
> Why do these two controllers have no power-domains ?
Bryan, on Eliza the videocc and camcc are connected on CX and MXA.
--
Thanks,
Taniya Das
On 10/04/2026 04:55, Taniya Das wrote:
>> Why do these two controllers have no power-domains ?
> Bryan, on Eliza the videocc and camcc are connected on CX and MXA.
Shouldn't you at least have:
power-domains = <&rpmhpd RPMHPD_CX> ?
And even
power-domains = <&rpmhpd RPMHPD_MX>,
<&rpmhpd RPMHPD_CX>;
power-domain-names = "mx",
"cx";
Konrad's suggestion to me was that MXA should have a vote in my CSIPHY
series I think he and Jagadeesh discussed it but I'm not sure if they
_concluded_ what was the right thing to do.
Right now I'm representing the dependency. MXA is always on ... and
there's nothing to do voting for it @ MX ?
---
bod
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