The GP1/GP2/GP3 clock sources are general-purpose timer/PWM clocks
that require runtime-computed MND divider values and duty cycle
control. They are currently using clk_rcg2_ops with a frequency table
containing only a few fixed entries (50/100/200 MHz), which:

- Cannot produce arbitrary frequencies needed for PWM periods
- Bypasses the MND divider (m=0, n=0), making duty cycle control
  impossible (MND is in bypass mode, set_duty_cycle returns -EINVAL)

Switch to clk_rcg2_gp_ops which uses clk_rcg2_calc_mnd() to
dynamically compute optimal M/N/pre_div values from any requested
frequency, and empty the frequency table since it is not used by the
GP ops path.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Sending this as RFC, because I'm not sure if all other gcc drivers require
the same change.
---
 drivers/clk/qcom/gcc-sc7280.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 4502926a2691..e7748c468721 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -457,9 +457,6 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 };
 
 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
-	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
-	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
-	F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
 	{ }
 };
 
@@ -473,7 +470,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
 		.name = "gcc_gp1_clk_src",
 		.parent_data = gcc_parent_data_4,
 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_gp_ops,
 	},
 };
 
@@ -487,7 +484,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
 		.name = "gcc_gp2_clk_src",
 		.parent_data = gcc_parent_data_4,
 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_gp_ops,
 	},
 };
 
@@ -501,7 +498,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
 		.name = "gcc_gp3_clk_src",
 		.parent_data = gcc_parent_data_4,
 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_gp_ops,
 	},
 };
 

---
base-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979
change-id: 20260406-gcc-gpclk-sc7280-2b412227c5fa

Best regards,
--  
Xilin Wu <sophon@radxa.com>

On 4/6/26 6:00 PM, Xilin Wu wrote:
> The GP1/GP2/GP3 clock sources are general-purpose timer/PWM clocks
> that require runtime-computed MND divider values and duty cycle
> control. They are currently using clk_rcg2_ops with a frequency table
> containing only a few fixed entries (50/100/200 MHz), which:
> 
> - Cannot produce arbitrary frequencies needed for PWM periods
> - Bypasses the MND divider (m=0, n=0), making duty cycle control
>   impossible (MND is in bypass mode, set_duty_cycle returns -EINVAL)
> 
> Switch to clk_rcg2_gp_ops which uses clk_rcg2_calc_mnd() to
> dynamically compute optimal M/N/pre_div values from any requested
> frequency, and empty the frequency table since it is not used by the
> GP ops path.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
> Sending this as RFC, because I'm not sure if all other gcc drivers require
> the same change.

Possibly!

It's only been introduced recently, so it may be that we do a mass update

However

The introductory commit notes:

 Limitations:
	- The driver doesn't select a parent clock (it may be selected by client
	in device tree with assigned-clocks, assigned-clock-parents properties)

which could potentially break some existing users that rely on the clock
provider to do it..

> ---
>  drivers/clk/qcom/gcc-sc7280.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
> index 4502926a2691..e7748c468721 100644
> --- a/drivers/clk/qcom/gcc-sc7280.c
> +++ b/drivers/clk/qcom/gcc-sc7280.c
> @@ -457,9 +457,6 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
>  };
>  
>  static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> -	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> -	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> -	F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
>  	{ }
>  };

I don't think any of the rcg2_gp ops use the frequency table, you
should be able to simply remove it

Konrad