arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++ arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+)
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index 2852d257ac8c..3fdf8dbbde02 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -560,6 +560,13 @@ &pon_resin {
status = "okay";
};
+&remoteproc_soccp {
+ firmware-name = "qcom/glymur/soccp.mbn",
+ "qcom/glymur/soccp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..f7f3374a5e08 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2264,6 +2264,53 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccpdtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "ping";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+
+ };
+ };
+
usb_hs_phy: phy@fa0000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
---
base-commit: bd0f139e5fc11182777b81cefc3893ea508544ec
change-id: 20260403-glymur-soccp-2ca25f3b30e2
prerequisite-message-id: <20260326-knp-soccp-dt-v1-0-a60c2ae36e9b@oss.qualcomm.com>
prerequisite-patch-id: fa390011ee531589a7ad14250d158f497622efbd
prerequisite-patch-id: 93e7fca58a5c06edefa624ec2b006dd80f4749a8
prerequisite-patch-id: 99a3b6a7fcd061267b40097ad25f652ebe0a4c7b
Best regards,
--
Ananthu C V <ananthu.cv@oss.qualcomm.com>On Fri, Apr 03, 2026 at 04:39:05AM -0700, Ananthu C V wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
Your commit is lacking both subject prefix and commit message.
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
v3? Where is the changelog?
> arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> index 2852d257ac8c..3fdf8dbbde02 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> @@ -560,6 +560,13 @@ &pon_resin {
> status = "okay";
> };
>
> +&remoteproc_soccp {
> + firmware-name = "qcom/glymur/soccp.mbn",
> + "qcom/glymur/soccp_dtb.mbn";
> +
> + status = "okay";
> +};
> +
> &tlmm {
> gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
> <10 2>, /* OOB UART */
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f23cf81ddb77..f7f3374a5e08 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2264,6 +2264,53 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
> + remoteproc_soccp: remoteproc-soccp@d00000 {
Isn't remoteproc@ sufficient?
> + compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
This binding hasn't been merged, and yet you don't mention that this
can't be merged?
> + reg = <0x0 0x00d00000 0x0 0x200000>;
> +
> + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog",
> + "fatal",
> + "ready",
> + "handover",
> + "stop-ack",
> + "pong";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>,
> + <&rpmhpd RPMHPD_MX>;
> + power-domain-names = "cx",
> + "mx";
> +
> + memory-region = <&soccp_mem>,
> + <&soccpdtb_mem>;
> +
> + qcom,smem-states = <&soccp_smp2p_out 0>,
> + <&soccp_smp2p_out 8>;
> + qcom,smem-state-names = "stop",
> + "ping";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_MPROC_SOCCP
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> + qcom,remote-pid = <19>;
> + label = "soccp";
> +
> + };
> + };
> +
> usb_hs_phy: phy@fa0000 {
> compatible = "qcom,glymur-m31-eusb2-phy",
> "qcom,sm8750-m31-eusb2-phy";
>
> ---
> base-commit: bd0f139e5fc11182777b81cefc3893ea508544ec
> change-id: 20260403-glymur-soccp-2ca25f3b30e2
> prerequisite-message-id: <20260326-knp-soccp-dt-v1-0-a60c2ae36e9b@oss.qualcomm.com>
> prerequisite-patch-id: fa390011ee531589a7ad14250d158f497622efbd
> prerequisite-patch-id: 93e7fca58a5c06edefa624ec2b006dd80f4749a8
> prerequisite-patch-id: 99a3b6a7fcd061267b40097ad25f652ebe0a4c7b
Why isn't this list empty?
Regards,
Bjorn
>
> Best regards,
> --
> Ananthu C V <ananthu.cv@oss.qualcomm.com>
>
Hi Bjorn,
On Fri, Apr 10, 2026 at 09:52:18PM -0500, Bjorn Andersson wrote:
> On Fri, Apr 03, 2026 at 04:39:05AM -0700, Ananthu C V wrote:
> > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >
>
> Your commit is lacking both subject prefix and commit message.
Yes, sorry for that. Some mess happened during the process, next revision will
have everything proper.
>
> > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
>
> v3? Where is the changelog?
This is also part of the aforementioned mess up, already taken care of for the
next revision prep.
> > arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++
> > 2 files changed, 54 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > index 2852d257ac8c..3fdf8dbbde02 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> > @@ -560,6 +560,13 @@ &pon_resin {
> > status = "okay";
> > };
> >
> > +&remoteproc_soccp {
> > + firmware-name = "qcom/glymur/soccp.mbn",
> > + "qcom/glymur/soccp_dtb.mbn";
> > +
> > + status = "okay";
> > +};
> > +
> > &tlmm {
> > gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
> > <10 2>, /* OOB UART */
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index f23cf81ddb77..f7f3374a5e08 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -2264,6 +2264,53 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> > };
> > };
> >
> > + remoteproc_soccp: remoteproc-soccp@d00000 {
>
> Isn't remoteproc@ sufficient?
ack.
>
> > + compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
>
> This binding hasn't been merged, and yet you don't mention that this
> can't be merged?
My understanding was that the prerequisite-***-id part would serve as the dependency.
I'll make sure to explicitly mention such cases in the future.
>
> > + reg = <0x0 0x00d00000 0x0 0x200000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "wdog",
> > + "fatal",
> > + "ready",
> > + "handover",
> > + "stop-ack",
> > + "pong";
> > +
> > + clocks = <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "xo";
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>,
> > + <&rpmhpd RPMHPD_MX>;
> > + power-domain-names = "cx",
> > + "mx";
> > +
> > + memory-region = <&soccp_mem>,
> > + <&soccpdtb_mem>;
> > +
> > + qcom,smem-states = <&soccp_smp2p_out 0>,
> > + <&soccp_smp2p_out 8>;
> > + qcom,smem-state-names = "stop",
> > + "ping";
> > +
> > + status = "disabled";
> > +
> > + glink-edge {
> > + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
> > + IPCC_MPROC_SIGNAL_GLINK_QMP
> > + IRQ_TYPE_EDGE_RISING>;
> > + mboxes = <&ipcc IPCC_MPROC_SOCCP
> > + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> > + qcom,remote-pid = <19>;
> > + label = "soccp";
> > +
> > + };
> > + };
> > +
> > usb_hs_phy: phy@fa0000 {
> > compatible = "qcom,glymur-m31-eusb2-phy",
> > "qcom,sm8750-m31-eusb2-phy";
> >
> > ---
> > base-commit: bd0f139e5fc11182777b81cefc3893ea508544ec
> > change-id: 20260403-glymur-soccp-2ca25f3b30e2
> > prerequisite-message-id: <20260326-knp-soccp-dt-v1-0-a60c2ae36e9b@oss.qualcomm.com>
> > prerequisite-patch-id: fa390011ee531589a7ad14250d158f497622efbd
> > prerequisite-patch-id: 93e7fca58a5c06edefa624ec2b006dd80f4749a8
> > prerequisite-patch-id: 99a3b6a7fcd061267b40097ad25f652ebe0a4c7b
>
> Why isn't this list empty?
As mentioned above, this was supposed to be the dependency, my bad for not mentioning it
explicitly.
>
> Regards,
> Bjorn
Thanks for the review, Bjorn. I'll probably wait until the driver changes are merged to
make another revision.
Best,
Ananthu
On 4/3/26 1:39 PM, Ananthu C V wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
[...]
> + remoteproc_soccp: remoteproc-soccp@d00000 {
remoteproc-soccp@ ->remoteproc@
> + compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
> + reg = <0x0 0x00d00000 0x0 0x200000>;
> +
> + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog",
> + "fatal",
> + "ready",
> + "handover",
> + "stop-ack",
> + "pong";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>,
> + <&rpmhpd RPMHPD_MX>;
> + power-domain-names = "cx",
> + "mx";
> +
> + memory-region = <&soccp_mem>,
> + <&soccpdtb_mem>;
> +
> + qcom,smem-states = <&soccp_smp2p_out 0>,
> + <&soccp_smp2p_out 8>;
> + qcom,smem-state-names = "stop",
> + "ping";
> +
> + status = "disabled";
Let's drop this line, no one should desire to run a system without SoCCP
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_MPROC_SOCCP
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> + qcom,remote-pid = <19>;
> + label = "soccp";
> +
> + };
Stray \n above
Konrad
On Tue, Apr 07, 2026 at 01:41:33PM +0200, Konrad Dybcio wrote:
> On 4/3/26 1:39 PM, Ananthu C V wrote:
> > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >
> > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + remoteproc_soccp: remoteproc-soccp@d00000 {
>
> remoteproc-soccp@ ->remoteproc@
ack
> > + compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
> > + reg = <0x0 0x00d00000 0x0 0x200000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> > + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "wdog",
> > + "fatal",
> > + "ready",
> > + "handover",
> > + "stop-ack",
> > + "pong";
> > +
> > + clocks = <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "xo";
> > +
> > + power-domains = <&rpmhpd RPMHPD_CX>,
> > + <&rpmhpd RPMHPD_MX>;
> > + power-domain-names = "cx",
> > + "mx";
> > +
> > + memory-region = <&soccp_mem>,
> > + <&soccpdtb_mem>;
> > +
> > + qcom,smem-states = <&soccp_smp2p_out 0>,
> > + <&soccp_smp2p_out 8>;
> > + qcom,smem-state-names = "stop",
> > + "ping";
> > +
> > + status = "disabled";
>
> Let's drop this line, no one should desire to run a system without SoCCP
ack, that makes sense.
> > +
> > + glink-edge {
> > + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
> > + IPCC_MPROC_SIGNAL_GLINK_QMP
> > + IRQ_TYPE_EDGE_RISING>;
> > + mboxes = <&ipcc IPCC_MPROC_SOCCP
> > + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> > + qcom,remote-pid = <19>;
> > + label = "soccp";
> > +
> > + };
>
> Stray \n above
noted, will fix.
> Konrad
Thanks for the review Konrad, will reflect the changes in the next revision.
Best,
Ananthu
On Fri, Apr 03, 2026 at 04:39:05AM -0700, Ananthu C V wrote: > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com> > > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> > Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++ > arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++ > 2 files changed, 54 insertions(+) Missing commit message. Also, as this is adding SocCP, can we get pmic glink device? -- With best wishes Dmitry
On Fri, Apr 03, 2026 at 11:25:50PM +0300, Dmitry Baryshkov wrote: > On Fri, Apr 03, 2026 at 04:39:05AM -0700, Ananthu C V wrote: > > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com> > > > > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> > > Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> > > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> > > --- > > arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++++ > > arch/arm64/boot/dts/qcom/glymur.dtsi | 47 ++++++++++++++++++++++++++++++++ > > 2 files changed, 54 insertions(+) > > Missing commit message. It appears trying out some b4 shenanigans messed this up, I'll fix it. > Also, as this is adding SocCP, can we get pmic glink device? pmic-glink for glymur is already present, in glymur-crd.dts. > -- > With best wishes > Dmitry Thank you for the review Dmitry, much appreciated. Best, Ananthu
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