Add devicetree changes to enable second Mobile Display Subsystem (mdss1),
Display Processing Unit(DPU), Display Port(DP), Display clock controller
(dispcc1) and eDP PHYs on the Qualcomm Lemans platform.
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++++++++++---
1 file changed, 262 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index bc0ec9a80284..4e608bd6486c 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5474,7 +5474,7 @@ mdss0_dp1: displayport-controller@af5c000 {
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
- operating-points-v2 = <&dp1_opp_table>;
+ operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#sound-dai-cells = <0>;
@@ -5499,30 +5499,6 @@ port@1 {
mdss0_dp1_out: endpoint { };
};
};
-
- dp1_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-162000000 {
- opp-hz = /bits/ 64 <162000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-270000000 {
- opp-hz = /bits/ 64 <270000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-540000000 {
- opp-hz = /bits/ 64 <540000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
-
- opp-810000000 {
- opp-hz = /bits/ 64 <810000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
};
};
@@ -7055,6 +7031,265 @@ compute-cb@3 {
};
};
+ mdss1: display-subsystem@22000000 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x22000000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1800 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ display-controller@22001000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x22001000 0x0 0x8f000>,
+ <0x0 0x220b0000 0x0 0x3000>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu1_intf0_out: endpoint {
+ remote-endpoint = <&mdss1_dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu1_intf4_out: endpoint {
+ remote-endpoint = <&mdss1_dp1_in>;
+ };
+ };
+ };
+ };
+
+ mdss1_dp0_phy: phy@220c2a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c2a00 0x0 0x200>,
+ <0x0 0x220c2200 0x0 0xd0>,
+ <0x0 0x220c2600 0x0 0xd0>,
+ <0x0 0x220c2000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@220c5a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c5a00 0x0 0x200>,
+ <0x0 0x220c5200 0x0 0xd0>,
+ <0x0 0x220c5600 0x0 0xd0>,
+ <0x0 0x220c5000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp0: displayport-controller@22154000 {
+ compatible = "qcom,sa8775p-dp";
+ reg = <0x0 0x22154000 0x0 0x104>,
+ <0x0 0x22154200 0x0 0x0c0>,
+ <0x0 0x22155000 0x0 0x770>,
+ <0x0 0x22156000 0x0 0x09c>,
+ <0x0 0x22157000 0x0 0x09c>,
+ <0x0 0x22158000 0x0 0x09c>,
+ <0x0 0x22159000 0x0 0x09c>,
+ <0x0 0x2215a000 0x0 0x23c>,
+ <0x0 0x2215b000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <12>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
+ phys = <&mdss1_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp0_in: endpoint {
+ remote-endpoint = <&dpu1_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp0_out: endpoint { };
+ };
+ };
+ };
+
+ mdss1_dp1: displayport-controller@2215c000 {
+ compatible = "qcom,sa8775p-dp";
+ reg = <0x0 0x2215c000 0x0 0x104>,
+ <0x0 0x2215c200 0x0 0x0c0>,
+ <0x0 0x2215d000 0x0 0x770>,
+ <0x0 0x2215e000 0x0 0x09c>,
+ <0x0 0x2215f000 0x0 0x09c>,
+ <0x0 0x22160000 0x0 0x09c>,
+ <0x0 0x22161000 0x0 0x09c>,
+ <0x0 0x22162000 0x0 0x23c>,
+ <0x0 0x22163000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <13>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
+ phys = <&mdss1_dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp1_in: endpoint {
+ remote-endpoint = <&dpu1_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp1_out: endpoint { };
+ };
+ };
+
+ };
+ };
+
dispcc1: clock-controller@22100000 {
compatible = "qcom,sa8775p-dispcc1";
reg = <0x0 0x22100000 0x0 0x20000>;
@@ -7062,13 +7297,13 @@ dispcc1: clock-controller@22100000 {
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
- <0>, <0>, <0>, <0>,
+ <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
+ <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- status = "disabled";
};
ethernet1: ethernet@23000000 {
--
2.34.1© 2016 - 2026 Red Hat, Inc.