From: Xuyang Dong <dongxuyang@eswincomputing.com>

The DesignWare PWM controller provides separate reset signals for each
clock domain, as specified in the hardware documentation. Without
asserting and deasserting these resets during probe, PWM outputs may
remain in an undefined state after system reboot.

To address this, the driver now supports an optional 'resets' property.
A full reset is performed only when no PWM channel is enabled, as
determined by reading the enable bit in each channel's control register.
This allows safe coexistence with bootloaders that have already
configured active PWM channels.

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml       | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
index 7523a89a1773..fd9f73c75121 100644
--- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
+++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
@@ -43,6 +43,9 @@ properties:
       - const: bus
       - const: timer
 
+  resets:
+    maxItems: 1
+
   snps,pwm-number:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: The number of PWM channels configured for this instance
-- 
2.34.1

On Thu, Apr 02, 2026 at 05:18:54PM +0800, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> The DesignWare PWM controller provides separate reset signals for each

So one controller has signals. Plural, right? Then why do you define
only one reset signal?

> clock domain, as specified in the hardware documentation. Without
> asserting and deasserting these resets during probe, PWM outputs may
> remain in an undefined state after system reboot.
> 
> To address this, the driver now supports an optional 'resets' property.

This is binding change, not driver.

> A full reset is performed only when no PWM channel is enabled, as
> determined by reading the enable bit in each channel's control register.

Do you describe hardware or driver behavior? This is not a change about
driver. Describe the hardware here - what is expected with that reset.

> This allows safe coexistence with bootloaders that have already
> configured active PWM channels.

Best regards,
Krzysztof