Add the GPIO node for the Realtek RTD1625 SoC.
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
arch/arm64/boot/dts/realtek/kent.dtsi | 43 ++++++++++++++++++++++++
arch/arm64/boot/dts/realtek/rtd1501.dtsi | 8 +++++
arch/arm64/boot/dts/realtek/rtd1861.dtsi | 8 +++++
arch/arm64/boot/dts/realtek/rtd1920.dtsi | 8 +++++
4 files changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
index 8d4293cd4c03..746932c26724 100644
--- a/arch/arm64/boot/dts/realtek/kent.dtsi
+++ b/arch/arm64/boot/dts/realtek/kent.dtsi
@@ -151,6 +151,39 @@ uart0: serial@7800 {
status = "disabled";
};
+ gpio: gpio@31100 {
+ compatible = "realtek,rtd1625-iso-gpio";
+ reg = <0x31100 0x398>,
+ <0x31000 0x100>;
+ gpio-controller;
+ gpio-ranges = <&isom_pinctrl 0 0 2>,
+ <&ve4_pinctrl 2 0 6>,
+ <&iso_pinctrl 8 0 4>,
+ <&ve4_pinctrl 12 6 2>,
+ <&main2_pinctrl 14 0 2>,
+ <&ve4_pinctrl 16 8 4>,
+ <&main2_pinctrl 20 2 3>,
+ <&ve4_pinctrl 23 12 3>,
+ <&iso_pinctrl 26 4 2>,
+ <&isom_pinctrl 28 2 2>,
+ <&ve4_pinctrl 30 15 6>,
+ <&main2_pinctrl 36 5 6>,
+ <&ve4_pinctrl 42 21 3>,
+ <&iso_pinctrl 45 6 6>,
+ <&ve4_pinctrl 51 24 1>,
+ <&iso_pinctrl 52 12 1>,
+ <&ve4_pinctrl 53 25 11>,
+ <&main2_pinctrl 64 11 28>,
+ <&ve4_pinctrl 92 36 2>,
+ <&iso_pinctrl 94 13 19>,
+ <&iso_pinctrl 128 32 4>,
+ <&ve4_pinctrl 132 38 13>,
+ <&iso_pinctrl 145 36 19>,
+ <&ve4_pinctrl 164 51 2>;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
iso_pinctrl: pinctrl@4e000 {
compatible = "realtek,rtd1625-iso-pinctrl";
reg = <0x4e000 0x1a4>;
@@ -161,6 +194,16 @@ main2_pinctrl: pinctrl@4f200 {
reg = <0x4f200 0x50>;
};
+ iso_m_gpio: gpio@89120 {
+ compatible = "realtek,rtd1625-isom-gpio";
+ reg = <0x89120 0x10>,
+ <0x89100 0x20>;
+ gpio-controller;
+ gpio-ranges = <&isom_pinctrl 0 0 4>;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
isom_pinctrl: pinctrl@146200 {
compatible = "realtek,rtd1625-isom-pinctrl";
reg = <0x146200 0x34>;
diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
index 65f7ede3df73..ae246a01f126 100644
--- a/arch/arm64/boot/dts/realtek/rtd1501.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
@@ -10,3 +10,11 @@
&uart0 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
+
+&iso_m_gpio {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts/realtek/rtd1861.dtsi
index 44c3de8f1f48..b5f08bdd9f17 100644
--- a/arch/arm64/boot/dts/realtek/rtd1861.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi
@@ -10,3 +10,11 @@
&uart0 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
+
+&iso_m_gpio {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts/realtek/rtd1920.dtsi
index becf546216e9..94c8a43916a8 100644
--- a/arch/arm64/boot/dts/realtek/rtd1920.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi
@@ -10,3 +10,11 @@
&uart0 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
+
+&iso_m_gpio {
+ status = "okay";
+};
--
2.34.1On Tue, Mar 31, 2026 at 07:38:34PM +0800, Yu-Chun Lin wrote:
> Add the GPIO node for the Realtek RTD1625 SoC.
>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> arch/arm64/boot/dts/realtek/kent.dtsi | 43 ++++++++++++++++++++++++
> arch/arm64/boot/dts/realtek/rtd1501.dtsi | 8 +++++
> arch/arm64/boot/dts/realtek/rtd1861.dtsi | 8 +++++
> arch/arm64/boot/dts/realtek/rtd1920.dtsi | 8 +++++
> 4 files changed, 67 insertions(+)
>
Why the DTS is in the middle? Drivers cannot depend on it. Please read
submitting patches (both documents).
> diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
> index 8d4293cd4c03..746932c26724 100644
> --- a/arch/arm64/boot/dts/realtek/kent.dtsi
> +++ b/arch/arm64/boot/dts/realtek/kent.dtsi
> @@ -151,6 +151,39 @@ uart0: serial@7800 {
> status = "disabled";
> };
>
> + gpio: gpio@31100 {
> + compatible = "realtek,rtd1625-iso-gpio";
> + reg = <0x31100 0x398>,
> + <0x31000 0x100>;
> + gpio-controller;
> + gpio-ranges = <&isom_pinctrl 0 0 2>,
> + <&ve4_pinctrl 2 0 6>,
> + <&iso_pinctrl 8 0 4>,
> + <&ve4_pinctrl 12 6 2>,
> + <&main2_pinctrl 14 0 2>,
> + <&ve4_pinctrl 16 8 4>,
> + <&main2_pinctrl 20 2 3>,
> + <&ve4_pinctrl 23 12 3>,
> + <&iso_pinctrl 26 4 2>,
> + <&isom_pinctrl 28 2 2>,
> + <&ve4_pinctrl 30 15 6>,
> + <&main2_pinctrl 36 5 6>,
> + <&ve4_pinctrl 42 21 3>,
> + <&iso_pinctrl 45 6 6>,
> + <&ve4_pinctrl 51 24 1>,
> + <&iso_pinctrl 52 12 1>,
> + <&ve4_pinctrl 53 25 11>,
> + <&main2_pinctrl 64 11 28>,
> + <&ve4_pinctrl 92 36 2>,
> + <&iso_pinctrl 94 13 19>,
> + <&iso_pinctrl 128 32 4>,
> + <&ve4_pinctrl 132 38 13>,
> + <&iso_pinctrl 145 36 19>,
> + <&ve4_pinctrl 164 51 2>;
> + #gpio-cells = <2>;
> + status = "disabled";
Why is it disabled? What is missing in the SoC? Which resources are
missing?
> + };
> +
> iso_pinctrl: pinctrl@4e000 {
> compatible = "realtek,rtd1625-iso-pinctrl";
> reg = <0x4e000 0x1a4>;
> @@ -161,6 +194,16 @@ main2_pinctrl: pinctrl@4f200 {
> reg = <0x4f200 0x50>;
> };
>
> + iso_m_gpio: gpio@89120 {
> + compatible = "realtek,rtd1625-isom-gpio";
> + reg = <0x89120 0x10>,
> + <0x89100 0x20>;
> + gpio-controller;
> + gpio-ranges = <&isom_pinctrl 0 0 4>;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> isom_pinctrl: pinctrl@146200 {
> compatible = "realtek,rtd1625-isom-pinctrl";
> reg = <0x146200 0x34>;
> diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
> index 65f7ede3df73..ae246a01f126 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1501.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
> @@ -10,3 +10,11 @@
> &uart0 {
> status = "okay";
> };
> +
> +&gpio {
Why aren't you following DTS coding style? What style is applicable for
Realtek?
Best regards,
Krzysztof
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