From: Alvin Šipraga <alsi@bang-olufsen.dk>
Add bridge port flags for:
- BR_LEARNING
- BR_FLOOD
- BR_MCAST_FLOOD
- BR_BCAST_FLOOD
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 125 +++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 0767b2704ad7..b26335c5b27e 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -302,6 +302,21 @@
#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
(0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
+/* Unknown unicast DA flooding port mask */
+#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG 0x0890
+#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_MASK 0x07FF
+
+/* Unknown multicast DA flooding port mask */
+#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG 0x0891
+#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_MASK 0x07FF
+
+/* Broadcast flooding port mask */
+#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG 0x0892
+#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_MASK 0x07FF
+
+#define RTL8365MB_SUPPORTED_BRIDGE_FLAGS \
+ (BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD)
+
/* Miscellaneous port configuration register, incl. VLAN egress mode */
#define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E
#define RTL8365MB_PORT_MISC_CFG_REG(_p) \
@@ -1641,6 +1656,97 @@ static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);
}
+static int rtl8365mb_port_set_ucast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ /* Frames with unknown unicast DA will be flooded to a programmable
+ * port mask that by default includes all ports. Add or remove
+ * the specified port from this port mask accordingly.
+ */
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_set_mcast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_set_bcast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct realtek_priv *priv = ds->priv;
+
+ dev_dbg(priv->dev, "pre_bridge_flags port:%d flags:%lx supported:%lx",
+ port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS);
+
+ if (flags.mask & ~RTL8365MB_SUPPORTED_BRIDGE_FLAGS)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rtl8365mb_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *exack)
+{
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ dev_dbg(priv->dev, "port_bridge_flags port:%d flags:%lx supported:%lx",
+ port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS);
+
+ if (flags.mask & BR_LEARNING) {
+ bool learning_en = !!(flags.val & BR_LEARNING);
+
+ ret = rtl8365mb_port_set_learning(priv, port, learning_en);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_FLOOD) {
+ bool ucast_flood_en = !!(flags.val & BR_FLOOD);
+
+ ret = rtl8365mb_port_set_ucast_flood(priv, port,
+ ucast_flood_en);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_MCAST_FLOOD) {
+ bool mcast_flood_en = !!(flags.val & BR_MCAST_FLOOD);
+
+ ret = rtl8365mb_port_set_mcast_flood(priv, port,
+ mcast_flood_en);
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_BCAST_FLOOD) {
+ bool bcast_flood_en = !!(flags.val & BR_BCAST_FLOOD);
+
+ ret = rtl8365mb_port_set_bcast_flood(priv, port,
+ bcast_flood_en);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port,
u32 efid)
{
@@ -1691,6 +1797,8 @@ static int rtl8365mb_port_bridge_join(struct dsa_switch *ds, int port,
int ret;
int i;
+ dev_dbg(priv->dev, "bridge %d join port %d\n", port, bridge.num);
+
/* Add this port to the isolation group of every other port
* offloading this bridge.
*/
@@ -1730,6 +1838,8 @@ static void rtl8365mb_port_bridge_leave(struct dsa_switch *ds, int port,
u32 mask = 0;
int i;
+ dev_dbg(priv->dev, "bridge %d leave port %d\n", port, bridge.num);
+
/* Remove this port from the isolation group of every other
* port offloading this bridge.
*/
@@ -2547,6 +2657,19 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ /* Enable all types of flooding */
+ ret = rtl8365mb_port_set_ucast_flood(priv, i, true);
+ if (ret)
+ goto out_teardown_irq;
+
+ ret = rtl8365mb_port_set_mcast_flood(priv, i, true);
+ if (ret)
+ goto out_teardown_irq;
+
+ ret = rtl8365mb_port_set_bcast_flood(priv, i, true);
+ if (ret)
+ goto out_teardown_irq;
+
/* Set up per-port private data */
p->priv = priv;
p->index = i;
@@ -2686,6 +2809,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.phylink_get_caps = rtl8365mb_phylink_get_caps,
.port_bridge_join = rtl8365mb_port_bridge_join,
.port_bridge_leave = rtl8365mb_port_bridge_leave,
+ .port_pre_bridge_flags = rtl8365mb_port_pre_bridge_flags,
+ .port_bridge_flags = rtl8365mb_port_bridge_flags,
.port_stp_state_set = rtl8365mb_port_stp_state_set,
.port_fast_age = rtl8365mb_port_fast_age,
.port_fdb_add = rtl8365mb_port_fdb_add,
--
2.53.0