Versal Gen2 platform multimedia integrated (MMI) module has a USB3.2 Gen
2x1 Dual Role Device IP. Introduce a new compatibility string to support
it. The USB wrapper registers reside in the MMI UDH system-level control
registers (SLCR) block, so instead of a dedicated reg property, add
xlnx,usb-syscon phandle with four cells specifying register offsets for
USB2 PHY, USB3 PHY, USB DRD, and USB power configuration within the SLCR.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
Changes for v2:
- Add blank line after compatible as suggested by Krzysztof.
- Retain the mmi suffix in the compatible string, as this USB 3.2 Gen2
IP from Synopsys is part of the dedicated Multimedia Interface. The
Versal Gen2 platform also includes a separate USB 2.0 controller,
and the mmi suffix uniquely distinguishes between the two USB
controllers. MMI is an independent subsystem particularly targeted for
deployment in Multi-Media related applications. The MMI block include
following submodules: UDH: USB3.2 Gen 2x1 Dual Role Device, DisplayPort
Transmit Controller, Security Module (ESM) for DisplayPort and HDMI
Controllers, DP AUX-I2C PHY.
- For MMI USB define parent address space i.e UDH block.
- Fix inconsistent MHz spacing to use SI convention with spaces.
- Move description before $ref and items in xlnx,usb-syscon property.
- Restore original zynqmp-dwc3 example, add new versal2-mmi-dwc3 example.
- Use 'usb' node name (without unit address) for versal2 example since
it has no reg property.
- Use 1/1 address/size configuration in versal2 example, use lowercase
hex in syscon offsets.
---
.../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 ++++++++++++++++++-
1 file changed, 67 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
index d6823ef5f9a7..5e31b961aff7 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
@@ -15,6 +15,8 @@ properties:
- enum:
- xlnx,zynqmp-dwc3
- xlnx,versal-dwc3
+ - xlnx,versal2-mmi-dwc3
+
reg:
maxItems: 1
@@ -37,8 +39,9 @@ properties:
A list of phandle and clock-specifier pairs for the clocks
listed in clock-names.
items:
- - description: Master/Core clock, has to be >= 125 MHz
- for SS operation and >= 60MHz for HS operation.
+ - description: Master/Core clock, has to be >= 156.25 MHz in SSP
+ mode, >= 125 MHz for SS operation and >= 60 MHz for HS
+ operation.
- description: Clock source to core during PHY power down.
clock-names:
@@ -79,6 +82,20 @@ properties:
description: GPIO used for the reset ulpi-phy
maxItems: 1
+ xlnx,usb-syscon:
+ description:
+ Phandle to the MMI UDH system-level control register (SLCR) syscon
+ node, with four cells specifying the register offsets for USB2 PHY,
+ USB3 PHY, USB DRD, and USB power configuration respectively.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to MMI UDH SLCR syscon node
+ - description: USB2 PHY register offset within SLCR
+ - description: USB3 PHY register offset within SLCR
+ - description: USB DRD register offset within SLCR
+ - description: USB power register offset within SLCR
+
# Required child node:
patternProperties:
@@ -87,7 +104,6 @@ patternProperties:
required:
- compatible
- - reg
- "#address-cells"
- "#size-cells"
- ranges
@@ -104,6 +120,7 @@ allOf:
contains:
enum:
- xlnx,versal-dwc3
+ - xlnx,versal2-mmi-dwc3
then:
properties:
resets:
@@ -117,6 +134,26 @@ allOf:
reset-names:
minItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,zynqmp-dwc3
+ - xlnx,versal-dwc3
+ then:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,versal2-mmi-dwc3
+ then:
+ required:
+ - xlnx,usb-syscon
+
additionalProperties: false
examples:
@@ -156,3 +193,30 @@ examples:
};
};
};
+ - |
+ #include <dt-bindings/power/xlnx-zynqmp-power.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+ #include <dt-bindings/phy/phy.h>
+ usb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,versal2-mmi-dwc3";
+ clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
+ clock-names = "bus_clk", "ref_clk";
+ power-domains = <&zynqmp_firmware PD_USB_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>;
+ reset-names = "usb_crst";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ phy-names = "usb3-phy";
+ xlnx,usb-syscon = <&udh_slcr 0x005c 0x0070 0x00c4 0x00f8>;
+ ranges;
+
+ usb@fe200000 {
+ compatible = "snps,dwc3";
+ reg = <0xfe200000 0x40000>;
+ interrupt-names = "host", "otg";
+ interrupts = <0 65 4>, <0 69 4>;
+ dr_mode = "host";
+ dma-coherent;
+ };
+ };
--
2.43.0On Tue, Mar 31, 2026 at 12:33:01AM +0530, Radhey Shyam Pandey wrote: > Versal Gen2 platform multimedia integrated (MMI) module has a USB3.2 Gen > 2x1 Dual Role Device IP. Introduce a new compatibility string to support > it. The USB wrapper registers reside in the MMI UDH system-level control > registers (SLCR) block, so instead of a dedicated reg property, add > xlnx,usb-syscon phandle with four cells specifying register offsets for > USB2 PHY, USB3 PHY, USB DRD, and USB power configuration within the SLCR. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > --- > Changes for v2: > - Add blank line after compatible as suggested by Krzysztof. > - Retain the mmi suffix in the compatible string, as this USB 3.2 Gen2 > IP from Synopsys is part of the dedicated Multimedia Interface. The > Versal Gen2 platform also includes a separate USB 2.0 controller, > and the mmi suffix uniquely distinguishes between the two USB > controllers. MMI is an independent subsystem particularly targeted for > deployment in Multi-Media related applications. The MMI block include > following submodules: UDH: USB3.2 Gen 2x1 Dual Role Device, DisplayPort > Transmit Controller, Security Module (ESM) for DisplayPort and HDMI > Controllers, DP AUX-I2C PHY. > - For MMI USB define parent address space i.e UDH block. > - Fix inconsistent MHz spacing to use SI convention with spaces. > - Move description before $ref and items in xlnx,usb-syscon property. > - Restore original zynqmp-dwc3 example, add new versal2-mmi-dwc3 example. > - Use 'usb' node name (without unit address) for versal2 example since > it has no reg property. > - Use 1/1 address/size configuration in versal2 example, use lowercase > hex in syscon offsets. > --- > .../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 ++++++++++++++++++- > 1 file changed, 67 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > index d6823ef5f9a7..5e31b961aff7 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml > @@ -15,6 +15,8 @@ properties: > - enum: > - xlnx,zynqmp-dwc3 > - xlnx,versal-dwc3 > + - xlnx,versal2-mmi-dwc3 I am not going to ask the same questions. Best regards, Krzysztof
> On Tue, Mar 31, 2026 at 12:33:01AM +0530, Radhey Shyam Pandey wrote: >> Versal Gen2 platform multimedia integrated (MMI) module has a USB3.2 Gen >> 2x1 Dual Role Device IP. Introduce a new compatibility string to support >> it. The USB wrapper registers reside in the MMI UDH system-level control >> registers (SLCR) block, so instead of a dedicated reg property, add >> xlnx,usb-syscon phandle with four cells specifying register offsets for >> USB2 PHY, USB3 PHY, USB DRD, and USB power configuration within the SLCR. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> --- >> Changes for v2: >> - Add blank line after compatible as suggested by Krzysztof. >> - Retain the mmi suffix in the compatible string, as this USB 3.2 Gen2 >> IP from Synopsys is part of the dedicated Multimedia Interface. The >> Versal Gen2 platform also includes a separate USB 2.0 controller, >> and the mmi suffix uniquely distinguishes between the two USB >> controllers. MMI is an independent subsystem particularly targeted for >> deployment in Multi-Media related applications. The MMI block include >> following submodules: UDH: USB3.2 Gen 2x1 Dual Role Device, DisplayPort >> Transmit Controller, Security Module (ESM) for DisplayPort and HDMI >> Controllers, DP AUX-I2C PHY. >> - For MMI USB define parent address space i.e UDH block. >> - Fix inconsistent MHz spacing to use SI convention with spaces. >> - Move description before $ref and items in xlnx,usb-syscon property. >> - Restore original zynqmp-dwc3 example, add new versal2-mmi-dwc3 example. >> - Use 'usb' node name (without unit address) for versal2 example since >> it has no reg property. >> - Use 1/1 address/size configuration in versal2 example, use lowercase >> hex in syscon offsets. >> --- >> .../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 ++++++++++++++++++- >> 1 file changed, 67 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml >> index d6823ef5f9a7..5e31b961aff7 100644 >> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml >> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml >> @@ -15,6 +15,8 @@ properties: >> - enum: >> - xlnx,zynqmp-dwc3 >> - xlnx,versal-dwc3 >> + - xlnx,versal2-mmi-dwc3 > I am not going to ask the same questions. I have provided the explanation in v2 changelog. Retain the mmi suffix in the compatible string, as this USB 3.2 Gen2 IP from Synopsys is part of the dedicated Multimedia Interface. The Versal Gen2 platform also includes a separate USB 2.0 controller, and the mmi suffix uniquely distinguishes between the two USB controllers. Let me know if you still have reservation in this approach (using <vendor>,<soc>-<subsystem>-<ip>). Or any other alternative based on IP version etc please suggest. Thanks, Radhey
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