From: Biju Das <biju.das.jz@bp.renesas.com>
Add I2C{0..3} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a08g046-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 13c158bb9215..a962b5ec6977 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -267,6 +267,14 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
DEF_COUPLED("eth1_rx_i_rmii",
R9A08G046_ETH1_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX11, 0x57c, 13,
MSTOP(BUS_PERI_COM, BIT(3))),
+ DEF_MOD("i2c0_pclk", R9A08G046_I2C0_PCLK, R9A08G046_CLK_P0, 0x580, 0,
+ MSTOP(BUS_MCPU2, BIT(10))),
+ DEF_MOD("i2c1_pclk", R9A08G046_I2C1_PCLK, R9A08G046_CLK_P0, 0x580, 1,
+ MSTOP(BUS_MCPU2, BIT(11))),
+ DEF_MOD("i2c2_pclk", R9A08G046_I2C2_PCLK, R9A08G046_CLK_P0, 0x580, 2,
+ MSTOP(BUS_MCPU2, BIT(12))),
+ DEF_MOD("i2c3_pclk", R9A08G046_I2C3_PCLK, R9A08G046_CLK_P0, 0x580, 3,
+ MSTOP(BUS_MCPU2, BIT(13))),
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
MSTOP(BUS_MCPU2, BIT(1))),
DEF_MOD("scif1_clk_pck", R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
@@ -292,6 +300,10 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
+ DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),
+ DEF_RST(R9A08G046_I2C1_MRST, 0x880, 1),
+ DEF_RST(R9A08G046_I2C2_MRST, 0x880, 2),
+ DEF_RST(R9A08G046_I2C3_MRST, 0x880, 3),
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),
--
2.43.0