From: Biju Das <biju.das.jz@bp.renesas.com>
Add SCIF{1..5} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a08g046-cpg.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 28d035613272..13c158bb9215 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -269,6 +269,16 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
MSTOP(BUS_PERI_COM, BIT(3))),
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
MSTOP(BUS_MCPU2, BIT(1))),
+ DEF_MOD("scif1_clk_pck", R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
+ MSTOP(BUS_MCPU2, BIT(2))),
+ DEF_MOD("scif2_clk_pck", R9A08G046_SCIF2_CLK_PCK, R9A08G046_CLK_P0, 0x584, 2,
+ MSTOP(BUS_MCPU2, BIT(3))),
+ DEF_MOD("scif3_clk_pck", R9A08G046_SCIF3_CLK_PCK, R9A08G046_CLK_P0, 0x584, 3,
+ MSTOP(BUS_MCPU2, BIT(4))),
+ DEF_MOD("scif4_clk_pck", R9A08G046_SCIF4_CLK_PCK, R9A08G046_CLK_P0, 0x584, 4,
+ MSTOP(BUS_MCPU2, BIT(5))),
+ DEF_MOD("scif5_clk_pck", R9A08G046_SCIF5_CLK_PCK, R9A08G046_CLK_P0, 0x584, 5,
+ MSTOP(BUS_MCPU3, BIT(4))),
DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
MSTOP(BUS_PERI_CPU, BIT(6))),
};
@@ -283,6 +293,11 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A08G046_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A08G046_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A08G046_SCIF5_RST_SYSTEM_N, 0x884, 5),
DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
--
2.43.0