For Intel, Centar, and Zhaoxin early init, use parsed CPUID(0x80000007)
instead of doing ugly bitwise operations on cpuinfo_x86::x86_power.

The latter is backed by a direct CPUID query and will be later removed.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/centaur.c |  4 +++-
 arch/x86/kernel/cpu/intel.c   | 13 +++++++------
 arch/x86/kernel/cpu/zhaoxin.c |  4 +++-
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 86cbe4427453..29688aec2231 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -89,6 +89,8 @@ enum {
 
 static void early_init_centaur(struct cpuinfo_x86 *c)
 {
+	const struct leaf_0x80000007_0 *el7 = cpuid_leaf(c, 0x80000007);
+
 #ifdef CONFIG_X86_32
 	/* Emulate MTRRs using Centaur's MCR. */
 	if (c->x86 == 5)
@@ -98,7 +100,7 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
 	    (c->x86 >= 7))
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 
-	if (c->x86_power & (1 << 8)) {
+	if (el7 && el7->constant_tsc) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7f186c68d701..e84042d1bbca 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -215,6 +215,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c)
 
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
+	const struct leaf_0x80000007_0 *el7 = cpuid_leaf(c, 0x80000007);
 	u64 misc_enable;
 
 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
@@ -262,16 +263,16 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		c->x86_phys_bits = 36;
 
 	/*
-	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
-	 * with P/T states and does not stop in deep C-states.
+	 * CPUID(0x80000007).constant_tsc implies that TSC runs at constant
+	 * rate with P/T states and does not stop in deep C-states
 	 *
-	 * It is also reliable across cores and sockets. (but not across
-	 * cabinets - we turn it off in that case explicitly.)
+	 * It is also reliable across cores and sockets, but not across
+	 * cabinets; disable it explicitly in that case.
 	 *
 	 * Use a model-specific check for some older CPUs that have invariant
-	 * TSC but may not report it architecturally via 8000_0007.
+	 * TSC but may not report it architecturally via CPUID(0x80000007).
 	 */
-	if (c->x86_power & (1 << 8)) {
+	if (el7 && el7->constant_tsc) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	} else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) ||
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index b068922efed9..5918f9387c87 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -50,10 +50,12 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
 
 static void early_init_zhaoxin(struct cpuinfo_x86 *c)
 {
+	const struct leaf_0x80000007_0 *el7 = cpuid_leaf(c, 0x80000007);
+
 	if (c->x86 >= 0x6)
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 
-	if (c->x86_power & (1 << 8)) {
+	if (el7 && el7->constant_tsc) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
-- 
2.53.0