On Fri, Mar 27, 2026 at 5:19 PM Jacopo Mondi
<jacopo.mondi@ideasonboard.com> wrote:
>
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>
> When the CRU is configured to use ICnSVC for virtual channel mapping,
> as on the RZ/{G3E, V2H/P} SoC, the ICnMC register must not be
> programmed.
>
> Return early after setting up ICnSVC to avoid overriding the ICnMC
> register, which is not applicable in this mode.
>
> This prevents unintended register programming when ICnSVC is enabled.
>
> Fixes: 3c5ca0a48bb0 ("media: rzg2l-cru: Drop function pointer to configure CSI")
> Cc: stable@vger.kernel.org
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> [Rework to not break image format programming]
> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
> ---
> .../media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h | 1 +
> drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c | 17 +++++++++++------
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h
> index a5a57369ef0e..10e62f2646d0 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h
> @@ -60,6 +60,7 @@
> #define ICnMC_CSCTHR BIT(5)
> #define ICnMC_INF(x) ((x) << 16)
> #define ICnMC_VCSEL(x) ((x) << 22)
> +#define ICnMC_VCSEL_MASK GENMASK(23, 22)
> #define ICnMC_INF_MASK GENMASK(21, 16)
>
> #define ICnMS_IA BIT(2)
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> index 162e2ace6931..6aea7c244df1 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> @@ -262,19 +262,24 @@ static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru,
> u8 csi_vc)
> {
> const struct rzg2l_cru_info *info = cru->info;
> - u32 icnmc = ICnMC_INF(ip_fmt->datatype);
> + u32 icnmc = rzg2l_cru_read(cru, info->image_conv) & ~(ICnMC_INF_MASK |
> + ICnMC_VCSEL_MASK);
> + icnmc |= ICnMC_INF(ip_fmt->datatype);
>
> + /*
> + * VC filtering goes through SVC register on G3E/V2H.
> + *
> + * FIXME: virtual channel filtering is likely broken and only VC=0
> + * works.
> + */
> if (cru->info->regs[ICnSVC]) {
> rzg2l_cru_write(cru, ICnSVCNUM, csi_vc);
> rzg2l_cru_write(cru, ICnSVC, ICnSVC_SVC0(0) | ICnSVC_SVC1(1) |
> ICnSVC_SVC2(2) | ICnSVC_SVC3(3));
> + } else {
> + icnmc |= ICnMC_VCSEL(csi_vc);
> }
>
> - icnmc |= rzg2l_cru_read(cru, info->image_conv) & ~ICnMC_INF_MASK;
> -
> - /* Set virtual channel CSI2 */
> - icnmc |= ICnMC_VCSEL(csi_vc);
> -
> rzg2l_cru_write(cru, info->image_conv, icnmc);
> }
>
>
> --
> 2.53.0
>
>