For CPSW9G QSGMII ports, CPSW assumes SERDES to be configured. Since it
may not be always true, add SERDES phys to guarantee it.

Fixes: 86e7de8bf908 ("arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode")
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is based on commit "0138af2472df" of origin/master branch
of Linux repo.

 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
index 8376fa4b6ee1..d403a3db0265 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
@@ -42,7 +42,8 @@ &cpsw0_port2 {
 	phy-handle = <&cpsw9g_phy1>;
 	phy-mode = "qsgmii";
 	mac-address = [00 00 00 00 00 00];
-	phys = <&cpsw0_phy_gmii_sel 2>;
+	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes0_qsgmii_link>;
+	phy-names = "mac", "serdes";
 };
 
 &cpsw0_port3 {
-- 
2.34.1

On Thu, 26 Mar 2026 12:52:37 +0530, Chintan Vankar <c-vankar@ti.com> wrote:
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> index 8376fa4b6ee1..d403a3db0265 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> @@ -42,7 +42,8 @@ &cpsw0_port2 {
>  	phy-handle = <&cpsw9g_phy1>;
>  	phy-mode = "qsgmii";
>  	mac-address = [00 00 00 00 00 00];
> -	phys = <&cpsw0_phy_gmii_sel 2>;
> +	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes0_qsgmii_link>;
> +	phy-names = "mac", "serdes";

Dont you need this for all the other ports as well, just like in J784s4
overlay?

-- 
Vignesh