Add the Tegra238 SoC device tree (tegra238.dtsi) and a minimal device
tree for the Tegra238 E2426-1099+E2423-1099 engineering reference
platform. The device-tree is not yet bootable and further enablement
will be added in follow-up patches.
Signed-off-by: Chun Ng <chunn@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile | 2 +
.../nvidia/tegra238-e2426-1099+e2423-1099.dts | 16 ++
arch/arm64/boot/dts/nvidia/tegra238.dtsi | 190 ++++++++++++++++++
3 files changed, 208 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
create mode 100644 arch/arm64/boot/dts/nvidia/tegra238.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index b139cbd14442..a5357809e222 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -13,6 +13,7 @@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@
DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@
DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@
DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@
+DTC_FLAGS_tegra238-e2426-1099+e2423-1099 := -@
DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@
dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
@@ -34,4 +35,5 @@ dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb
+dtb-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra238-e2426-1099+e2423-1099.dtb
dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
new file mode 100644
index 000000000000..d69ea2114e23
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+/dts-v1/;
+
+#include "tegra238.dtsi"
+
+/ {
+ model = "NVIDIA Tegra238 E2426-1099+E2423-1099";
+ compatible = "nvidia,e2426-1099+e2423-1099", "nvidia,tegra238";
+
+ bus@0 {
+ uarta: serial@3100000 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra238.dtsi b/arch/arm64/boot/dts/nvidia/tegra238.dtsi
new file mode 100644
index 000000000000..0570c3b20e62
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra238.dtsi
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#include <dt-bindings/clock/nvidia,tegra238.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/nvidia,tegra238.h>
+
+/ {
+ compatible = "nvidia,tegra238";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ bus@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ uarta: serial@3100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA238_CLK_UARTA>,
+ <&bpmp TEGRA238_CLK_PLLP_OUT0>;
+ clock-names = "uartclk", "apb_pclk";
+ assigned-clocks = <&bpmp TEGRA238_CLK_UARTA>;
+ assigned-clock-parents = <&bpmp TEGRA238_CLK_PLLP_OUT0>;
+ resets = <&bpmp TEGRA238_RESET_UARTA>;
+ arm,primecell-periphid = <0x00051011>;
+ status = "disabled";
+ };
+
+ fuse@3810000 {
+ compatible = "nvidia,tegra234-efuse";
+ reg = <0x0 0x03810000 0x0 0x19000>;
+ clocks = <&bpmp TEGRA238_CLK_FUSE>;
+ clock-names = "fuse";
+ };
+
+ hsp_top0: tegra-hsp@3c00000 {
+ compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
+ reg = <0x0 0x03c00000 0x0 0x000a0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell", "shared0";
+ #mbox-cells = <2>;
+ };
+
+ hsp_top1: tegra-hsp@3d00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x0 0x03d00000 0x0 0x000a0000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "shared0";
+ #mbox-cells = <2>;
+ };
+
+ aon_hsp: tegra-hsp@c150000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x0 0x0c150000 0x0 0x00090000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "shared1";
+ };
+
+ gic: interrupt-controller@f400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ #redistributor-regions = <1>;
+ interrupt-controller;
+ reg = <0x0 0x0f400000 0x0 0x00010000 /* GICD */
+ 0x0 0x0f440000 0x0 0x00200000>; /* GICR CPU 0-15 */
+ };
+
+ sram@40000000 {
+ compatible = "nvidia,tegra234-sysram", "mmio-sram";
+ reg = <0x0 0x40000000 0x0 0x72000>;
+ ranges = <0x0 0x0 0x40000000 0x72000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ no-memory-wc;
+
+ cpu_bpmp_tx: sram@70000 {
+ reg = <0x70000 0x1000>;
+ label = "cpu-bpmp-tx";
+ pool;
+ };
+
+ cpu_bpmp_rx: sram@71000 {
+ reg = <0x71000 0x1000>;
+ label = "cpu-bpmp-rx";
+ pool;
+ };
+ };
+ };
+
+ bpmp: bpmp {
+ compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
+ shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ bpmp_i2c: i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0_0: cpu@0 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x000>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_1: cpu@1 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x100>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_2: cpu@2 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x200>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_3: cpu@3 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x300>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_4: cpu@4 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x400>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_5: cpu@5 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x500>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_6: cpu@6 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x600>;
+
+ enable-method = "psci";
+ };
+
+ cpu0_7: cpu@7 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x700>;
+
+ enable-method = "psci";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.43.0On Wed, Mar 25, 2026 at 09:26:28PM +0000, Chun Ng wrote:
> Add the Tegra238 SoC device tree (tegra238.dtsi) and a minimal device
> tree for the Tegra238 E2426-1099+E2423-1099 engineering reference
> platform. The device-tree is not yet bootable and further enablement
Then drop it. If this cannot be booted then it is pointless in the
kernel, no benefit, no one can ever use it.
> will be added in follow-up patches.
>
> Signed-off-by: Chun Ng <chunn@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/Makefile | 2 +
> .../nvidia/tegra238-e2426-1099+e2423-1099.dts | 16 ++
> arch/arm64/boot/dts/nvidia/tegra238.dtsi | 190 ++++++++++++++++++
> 3 files changed, 208 insertions(+)
> create mode 100644 arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
> create mode 100644 arch/arm64/boot/dts/nvidia/tegra238.dtsi
>
> diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
> index b139cbd14442..a5357809e222 100644
> --- a/arch/arm64/boot/dts/nvidia/Makefile
> +++ b/arch/arm64/boot/dts/nvidia/Makefile
> @@ -13,6 +13,7 @@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@
> DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@
> DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@
> DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@
> +DTC_FLAGS_tegra238-e2426-1099+e2423-1099 := -@
> DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@
>
> dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
> @@ -34,4 +35,5 @@ dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
> dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb
> dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb
> dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb
> +dtb-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra238-e2426-1099+e2423-1099.dtb
> dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb
> diff --git a/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
> new file mode 100644
> index 000000000000..d69ea2114e23
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +
> +/dts-v1/;
> +
> +#include "tegra238.dtsi"
> +
> +/ {
> + model = "NVIDIA Tegra238 E2426-1099+E2423-1099";
> + compatible = "nvidia,e2426-1099+e2423-1099", "nvidia,tegra238";
> +
> + bus@0 {
> + uarta: serial@3100000 {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/nvidia/tegra238.dtsi b/arch/arm64/boot/dts/nvidia/tegra238.dtsi
> new file mode 100644
> index 000000000000..0570c3b20e62
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra238.dtsi
> @@ -0,0 +1,190 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +
> +#include <dt-bindings/clock/nvidia,tegra238.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/tegra186-hsp.h>
> +#include <dt-bindings/reset/nvidia,tegra238.h>
> +
> +/ {
> + compatible = "nvidia,tegra238";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + bus@0 {
> + compatible = "simple-bus";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>;
> +
> + uarta: serial@3100000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&bpmp TEGRA238_CLK_UARTA>,
> + <&bpmp TEGRA238_CLK_PLLP_OUT0>;
> + clock-names = "uartclk", "apb_pclk";
> + assigned-clocks = <&bpmp TEGRA238_CLK_UARTA>;
> + assigned-clock-parents = <&bpmp TEGRA238_CLK_PLLP_OUT0>;
> + resets = <&bpmp TEGRA238_RESET_UARTA>;
> + arm,primecell-periphid = <0x00051011>;
> + status = "disabled";
> + };
> +
> + fuse@3810000 {
> + compatible = "nvidia,tegra234-efuse";
> + reg = <0x0 0x03810000 0x0 0x19000>;
> + clocks = <&bpmp TEGRA238_CLK_FUSE>;
> + clock-names = "fuse";
> + };
> +
> + hsp_top0: tegra-hsp@3c00000 {
> + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
DTSI says 238, compatible says 234.
Best regards,
Krzysztof
On Thu, Mar 26, 2026 at 11:18:17AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Mar 25, 2026 at 09:26:28PM +0000, Chun Ng wrote:
> > Add the Tegra238 SoC device tree (tegra238.dtsi) and a minimal device
> > tree for the Tegra238 E2426-1099+E2423-1099 engineering reference
> > platform. The device-tree is not yet bootable and further enablement
>
> Then drop it. If this cannot be booted then it is pointless in the
> kernel, no benefit, no one can ever use it.
The purpose of this series is to establish a common baseline that people
can use to work on top off. We expect the non-bootable state to be very
temporary, but for practical reasons I want to get this merged so we can
make quicker progress.
[...]
> > + hsp_top0: tegra-hsp@3c00000 {
> > + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
>
> DTSI says 238, compatible says 234.
Tegra238 is a derivative of Tegra234, so there's even more similarities
than we typically have across generational gaps. Your recent comments
suggested that you'd like to see new compatible strings no matter how
minimal (or even non-existent) the differences might be, so I suppose we
could prepend a Tegra238-specific compatible to this.
Thierry
On 26/03/2026 12:03, Thierry Reding wrote: > On Thu, Mar 26, 2026 at 11:18:17AM +0100, Krzysztof Kozlowski wrote: >> On Wed, Mar 25, 2026 at 09:26:28PM +0000, Chun Ng wrote: >>> Add the Tegra238 SoC device tree (tegra238.dtsi) and a minimal device >>> tree for the Tegra238 E2426-1099+E2423-1099 engineering reference >>> platform. The device-tree is not yet bootable and further enablement >> >> Then drop it. If this cannot be booted then it is pointless in the >> kernel, no benefit, no one can ever use it. > > The purpose of this series is to establish a common baseline that people > can use to work on top off. We expect the non-bootable state to be very > temporary, but for practical reasons I want to get this merged so we can > make quicker progress. If this cannot be booted, then there are no practical reasons - no one will be able to develop on top of it. The only way anyone could use it is to have additional patch on top, to make it booting. Thus if you have already patches on top, which you need to share with every team/person, then you can as well share this one. What is the benefit for the community of having this patch in the kernel? = Best regards, Krzysztof
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