From: Biju Das <biju.das.jz@bp.renesas.com>
The IRQC block on RZ/G3L SoC is almost identical to one found on the
RZ/G3S SoC with the difference like it support more external interrupts,
GPT error Interrupts and also has additional registers for GPT/MTU
interrupt selection, shared interrupt selection between external interrupt
and TINT.
It has 16 external interrupts of which 8 interrupts are shared with
TINT[24:31] and are mutually exclusive. The external IRQ/TINT interrupt
selection is based on a register in the ICU block.
Ref:
v6: https://lore.kernel.org/all/20260322122421.132474-1-biju.das.jz@bp.renesas.com/
v5: https://lore.kernel.org/all/20260311192459.609064-1-biju.das.jz@bp.renesas.com/
v4: https://lore.kernel.org/all/20260227140316.308106-1-biju.das.jz@bp.renesas.com/
v3: https://lore.kernel.org/all/20260206111658.231934-1-biju.das.jz@bp.renesas.com/
v2: https://lore.kernel.org/all/20260204180632.249139-1-biju.das.jz@bp.renesas.com/
v1: https://lore.kernel.org/all/20260204142320.103184-1-biju.das.jz@bp.renesas.com/
v6->v7:
* Added a patch to fix error path in irq_domain_create_hierarchy()
* Replaced variable type of iitseln, sense, tmp in rzg2l_irq_set_type()
to unsigned int.
* Replaced rzg2l_irq_*and_get_irq_num()->rzg2l_irqc_*and_get_irq_num().
* Replaced raw_spinlock->raw_spinlock_irqsave in rzg2l_irqc_set_inttsel()
to avoid possible dead lock with the consumer driver probe and eoi
handler executing on the same cpu.
* Updated error handling paths in rzg2l_irqc_alloc()
* Added missing colon reported by the bot for 'struct member 'used_irqs'
not described in 'rzg2l_irqc_priv'.
v5->v6:
* Collected tag for binding patch#2
* Updated commit description for patch#5,#7,#8,#9,#12and#15
* Simplified rzg2l_irqc_{irq,tint}_eoi() by replacing raw_spin_lock
locking/unlocking with scoped_guard().
* Updated the variable type of offset, tssr_offset, and tssr_index to
unsigned int, in rzfive_irqc_irq_enable() as these variables are used
only for calculation.
* Simplified rzfive_irqc_irq_enable() by replacing raw_spin_lock
locking/unlocking with guard().
* Simplified rzfive_{irq,tint}_endisable by replacing raw_spin_lock
locking/unlocking with guard().
* Updated the variable type of offset, tssr_offset, and tssr_index to
unsigned int, in rzfive_tint_endisable() as these variables are used
only for calculation.
* Dropped stray newline in rzfive_tint_endisable().
* Simplified rzfive_irqc_{irq,tint}_{mask,unmask}() by replacing
raw_spin_lock locking/unlocking with scoped_guard().
* Updated the variable type of titseln, tssr_offset, tssr_index, index,
and sense to unsigned int, in rzg2l_tint_set_edge() as these variables
are used only for calculation.
* Switched to using irq_domain_ops::{alloc,free} callbacks for mutual
exclusion between external interrupts and GPIO interrupts as using
irq_{request,release}_resources() leading to irq storm()
* Dropped irq_{request,release}_resources().
* Replaced the macro TINTSEL->INTTSEL_TINTSEL
* Added macros INTTSEL_TINTSEL_START, IRQC_SHARED_IRQ_COUNT and
IRQC_IRQ_SHARED_START.
* Added used_irqs bitmap to struct rzg2l_irqc_priv to track allocation
state of shared_interrupt
* Added rzg2l_irqc_set_inttsel() for configuring INTTSEL register.
* Replaced irq_domain_free_irqs_common()->rzg2l_irqc_free() as
rzg2l_irqc_domain_ops::free() callback.
* Replaced the 8->IRQC_SHARED_IRQ_COUNT in shared_irq_cnt varaible as
the same macro used in bitmap.
v4->v5:
* Added support for separate interrupt chips so that the decision is made
at setup time and not at every interrupt delivery in the hotpath.
* Dropped the hw_irq range check involving info.{num_irq,tint_start,
irq_count}
* Updated rzg3l_irqc_probe() for supporting separate interrupt chips.
* Added callback irq_{request,release}_resources() to both irq and tint
interrupt chips.
* Dropped SoC dtsi patch from this series, will post later.
v3->v4:
* Collected tag from Rob for binding patch#1
* Updated commit description for binding patch#{1,2}.
* Updated commit header for patch#3
* Replaced IRQs->interrupts in commit description
* Fixed the typo Dynamicaly->Dynamically
* Updated commit description IRQs->interrupts in patch#4
* Replaced the variable type for num_irq in struct rzg2l_hw_info from
u8->unsigned int
* Replaced the pointer variable info from irqc_priv and instead embed a
struct hwinfo into irqc_priv and copy the data into it at probe time.
* Replaced the check 'hwirq > (priv->info->num_irq - 1)' with
hwirq >= priv->info.num_irq
* Updated commit description 'this differences->this difference' in
patch#5.
* Updated tint_start variable type from u8-> unsigned int.
* Updated commit description IRQs->interrupts in patch#6.
* Updated variable type of irq_count from u8->unsigned int.
* Updated commit description IRQs->interrupts in patch#7.
* Updated rzg2l_disable_tint_and_set_tint_source() for making
tint assignment very clear in the code.
* Formatted rzg3l_tssel_lut as table format.
* Updated commit header irq->interrupt in patch#8.
* Updated commit description IRQs->interrupts.
* Updated shared_irq_cnt variable type from u8->unsigned int.
v2->v3:
* Dropped items and instead used enum for single compatible values
* Add minItems for interrupts and interrupt-names properties of
the RZ/{G2L,G2UL,Five,V2L} SoCs
* Replaced maxItems->minItems for interrupts and interrupt-names
properties of the RZ/G3L SoC.
v1->v2:
* Simplified the binding by using pattern for intterrupt-names
* Fixed the binding warnings reported by bot.
Biju Das (16):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
interrupt-names
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
SoC
irqchip/renesas-rzg2l: Fix error path in irq_domain_create_hierarchy()
irqchip/renesas-rzg2l: Drop redundant IRQC_TINT_START check in
rzg2l_irqc_alloc()
irqchip/renesas-rzg2l: Replace single irq_chip with per-region
irq_chip instances
irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT
functions
irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and
TINT functions
irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with
TINT-specific handlers
irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate
IRQ and TINT helpers
irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate
IRQ and TINT handlers
irqchip/renesas-rzg2l: Dynamically allocate fwspec array
irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
irqchip/renesas-rzg2l: Add RZ/G3L support
irqchip/renesas-rzg2l: Add shared interrupt support
.../renesas,rzg2l-irqc.yaml | 157 ++----
drivers/irqchip/irq-renesas-rzg2l.c | 481 ++++++++++++++----
2 files changed, 427 insertions(+), 211 deletions(-)
--
2.43.0