From: Yi-Wei Wang <yiweiw@nvidia.com>
The clock driving the Tegra PWM IP can be sourced from different parent
clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based
upon the current parent clock that can be specified via device-tree.
After this, the Tegra194 SoC data becomes redundant, so get rid of it.
Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com>
Co-developed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
drivers/pwm/pwm-tegra.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 172063b51d44..759b98b97b6e 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -59,9 +59,6 @@
struct tegra_pwm_soc {
unsigned int num_channels;
-
- /* Maximum IP frequency for given SoCs */
- unsigned long max_frequency;
};
struct tegra_pwm_chip {
@@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)
return ret;
/* Set maximum frequency of the IP */
- ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);
+ ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
goto put_pm;
@@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)
/* Set minimum limit of PWM period for the IP */
pc->min_period_ns =
- (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
+ (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;
pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
if (IS_ERR(pc->rst)) {
@@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
static const struct tegra_pwm_soc tegra20_pwm_soc = {
.num_channels = 4,
- .max_frequency = 48000000UL,
};
static const struct tegra_pwm_soc tegra186_pwm_soc = {
.num_channels = 1,
- .max_frequency = 102000000UL,
-};
-
-static const struct tegra_pwm_soc tegra194_pwm_soc = {
- .num_channels = 1,
- .max_frequency = 408000000UL,
};
static const struct of_device_id tegra_pwm_of_match[] = {
{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
- { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
+ { .compatible = "nvidia,tegra194-pwm", .data = &tegra186_pwm_soc },
{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
--
2.53.0Hi Mikko,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356
base: 11439c4635edd669ae435eec308f4ab8a0804808
patch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com
patch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
config: hexagon-randconfig-r113-20260330 (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 2cd67b8b69f78e3f95918204320c3075a74ba16c)
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302251.AFXspVqF-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603302251.AFXspVqF-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/pwm/pwm-tegra.c:303:47: sparse: sparse: cast truncates bits from constant value (7fffffffffffffff becomes ffffffff)
vim +303 drivers/pwm/pwm-tegra.c
266
267 static int tegra_pwm_probe(struct platform_device *pdev)
268 {
269 struct pwm_chip *chip;
270 struct tegra_pwm_chip *pc;
271 const struct tegra_pwm_soc *soc;
272 int ret;
273
274 soc = of_device_get_match_data(&pdev->dev);
275
276 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));
277 if (IS_ERR(chip))
278 return PTR_ERR(chip);
279 pc = to_tegra_pwm_chip(chip);
280
281 pc->soc = soc;
282
283 pc->regs = devm_platform_ioremap_resource(pdev, 0);
284 if (IS_ERR(pc->regs))
285 return PTR_ERR(pc->regs);
286
287 platform_set_drvdata(pdev, chip);
288
289 pc->clk = devm_clk_get(&pdev->dev, NULL);
290 if (IS_ERR(pc->clk))
291 return PTR_ERR(pc->clk);
292
293 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
294 if (ret)
295 return ret;
296
297 pm_runtime_enable(&pdev->dev);
298 ret = pm_runtime_resume_and_get(&pdev->dev);
299 if (ret)
300 return ret;
301
302 /* Set maximum frequency of the IP */
> 303 ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);
304 if (ret < 0) {
305 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
306 goto put_pm;
307 }
308
309 /*
310 * The requested and configured frequency may differ due to
311 * clock register resolutions. Get the configured frequency
312 * so that PWM period can be calculated more accurately.
313 */
314 pc->clk_rate = clk_get_rate(pc->clk);
315
316 /* Set minimum limit of PWM period for the IP */
317 pc->min_period_ns =
318 (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;
319
320 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
321 if (IS_ERR(pc->rst)) {
322 ret = PTR_ERR(pc->rst);
323 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
324 goto put_pm;
325 }
326
327 reset_control_deassert(pc->rst);
328
329 chip->ops = &tegra_pwm_ops;
330
331 ret = pwmchip_add(chip);
332 if (ret < 0) {
333 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
334 reset_control_assert(pc->rst);
335 goto put_pm;
336 }
337
338 pm_runtime_put(&pdev->dev);
339
340 return 0;
341 put_pm:
342 pm_runtime_put_sync_suspend(&pdev->dev);
343 pm_runtime_force_suspend(&pdev->dev);
344 return ret;
345 }
346
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Mikko,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 11439c4635edd669ae435eec308f4ab8a0804808]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/dt-bindings-pwm-Document-Tegra194-and-Tegra264-controllers/20260329-233356
base: 11439c4635edd669ae435eec308f4ab8a0804808
patch link: https://lore.kernel.org/r/20260325-t264-pwm-v2-2-998d885984b3%40nvidia.com
patch subject: [PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency
config: nios2-allmodconfig (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260330/202603302259.NdAkuCVx-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603302259.NdAkuCVx-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:17,
from include/linux/clk.h:13,
from drivers/pwm/pwm-tegra.c:39:
drivers/pwm/pwm-tegra.c: In function 'tegra_pwm_probe':
>> include/linux/limits.h:26:25: warning: unsigned conversion from 'long long int' to 'long unsigned int' changes value from '9223372036854775807' to '4294967295' [-Woverflow]
26 | #define S64_MAX ((s64)(U64_MAX >> 1))
| ^~~~~~~~~~~~~~~~~~~~~
drivers/pwm/pwm-tegra.c:303:47: note: in expansion of macro 'S64_MAX'
303 | ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);
| ^~~~~~~
vim +26 include/linux/limits.h
3c9d017cc283df Andy Shevchenko 2023-08-04 14
54d50897d544c8 Masahiro Yamada 2019-03-07 15 #define U8_MAX ((u8)~0U)
54d50897d544c8 Masahiro Yamada 2019-03-07 16 #define S8_MAX ((s8)(U8_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 17 #define S8_MIN ((s8)(-S8_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 18 #define U16_MAX ((u16)~0U)
54d50897d544c8 Masahiro Yamada 2019-03-07 19 #define S16_MAX ((s16)(U16_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 20 #define S16_MIN ((s16)(-S16_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 21 #define U32_MAX ((u32)~0U)
3f50f132d8400e John Fastabend 2020-03-30 22 #define U32_MIN ((u32)0)
54d50897d544c8 Masahiro Yamada 2019-03-07 23 #define S32_MAX ((s32)(U32_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 24 #define S32_MIN ((s32)(-S32_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 25 #define U64_MAX ((u64)~0ULL)
54d50897d544c8 Masahiro Yamada 2019-03-07 @26 #define S64_MAX ((s64)(U64_MAX >> 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 27 #define S64_MIN ((s64)(-S64_MAX - 1))
54d50897d544c8 Masahiro Yamada 2019-03-07 28
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Wed, Mar 25, 2026 at 07:17:00PM +0900, Mikko Perttunen wrote: > From: Yi-Wei Wang <yiweiw@nvidia.com> > > The clock driving the Tegra PWM IP can be sourced from different parent > clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based > upon the current parent clock that can be specified via device-tree. > > After this, the Tegra194 SoC data becomes redundant, so get rid of it. > > Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com> > Co-developed-by: Mikko Perttunen <mperttunen@nvidia.com> > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > drivers/pwm/pwm-tegra.c | 16 +++------------- > 1 file changed, 3 insertions(+), 13 deletions(-) Reviewed-by: Thierry Reding <treding@nvidia.com>
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