From: Jackson Lee <jackson.lee@chipsnmedia.com>
Constrained Baseline Profile (CBP) and Baseline Profile (BP) have been
treated as the same.
Introduce the ability to differentiate between the two.
Fixes: 9707a6254a8a ("media: chips-media: wave5: Add the v4l2 layer")
Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
---
drivers/media/platform/chips-media/wave5/wave5-hw.c | 3 +++
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 5 ++++-
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
index c516d125f553..2392bce8d840 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
@@ -1763,6 +1763,9 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
(p_param->skip_intra_trans << 25) |
(p_param->strong_intra_smooth_enable << 27) |
(p_param->en_still_picture << 30);
+ else if (inst->std == W_AVC_ENC)
+ reg_val |= (p_param->constraint_set1_flag << 29);
+
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);
reg_val = (p_param->lossless_enable) |
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
index 6fe01217233f..775beeb10fd4 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
@@ -939,6 +939,8 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
inst->enc_param.profile = H264_PROFILE_BP;
inst->bit_depth = 8;
+ if (ctrl->val == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE)
+ inst->enc_param.constraint_set1_flag = 1;
break;
case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
inst->enc_param.profile = H264_PROFILE_MP;
@@ -1215,6 +1217,7 @@ static int wave5_set_enc_openparam(struct enc_open_param *open_param,
open_param->wave_param.intra_period = input.avc_idr_period;
}
} else {
+ open_param->wave_param.constraint_set1_flag = input.constraint_set1_flag;
open_param->wave_param.avc_idr_period = input.avc_idr_period;
}
open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode;
@@ -1687,7 +1690,7 @@ static int wave5_vpu_open_enc(struct file *filp)
-6, 6, 1, 0);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
- 0, 1, 1, 1);
+ 0, 1, 1, 0);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION,
0, 1, 1, 0);
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
index dc31689e0d27..7b08fef58217 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
@@ -570,6 +570,7 @@ struct enc_wave_param {
u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
+ u32 constraint_set1_flag: 1; /* enable CBP */
u32 bg_detection: 1; /* enable background detection */
};
--
2.43.0
Hi Jackson,
On 3/24/26 00:03, Jackson.lee wrote:
> From: Jackson Lee <jackson.lee@chipsnmedia.com>
>
> Constrained Baseline Profile (CBP) and Baseline Profile (BP) have been
> treated as the same.
> Introduce the ability to differentiate between the two.
>
> Fixes: 9707a6254a8a ("media: chips-media: wave5: Add the v4l2 layer")
> Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
> ---
> drivers/media/platform/chips-media/wave5/wave5-hw.c | 3 +++
> drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c | 5 ++++-
> drivers/media/platform/chips-media/wave5/wave5-vpuapi.h | 1 +
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> index c516d125f553..2392bce8d840 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
> @@ -1763,6 +1763,9 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
> (p_param->skip_intra_trans << 25) |
> (p_param->strong_intra_smooth_enable << 27) |
> (p_param->en_still_picture << 30);
> + else if (inst->std == W_AVC_ENC)
> + reg_val |= (p_param->constraint_set1_flag << 29);
> +
> vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);
>
> reg_val = (p_param->lossless_enable) |
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> index 6fe01217233f..775beeb10fd4 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
> @@ -939,6 +939,8 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
> case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
> inst->enc_param.profile = H264_PROFILE_BP;
> inst->bit_depth = 8;
> + if (ctrl->val == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE)
> + inst->enc_param.constraint_set1_flag = 1;
> break;
> case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
> inst->enc_param.profile = H264_PROFILE_MP;
> @@ -1215,6 +1217,7 @@ static int wave5_set_enc_openparam(struct enc_open_param *open_param,
> open_param->wave_param.intra_period = input.avc_idr_period;
> }
> } else {
> + open_param->wave_param.constraint_set1_flag = input.constraint_set1_flag;
> open_param->wave_param.avc_idr_period = input.avc_idr_period;
> }
Thank you for fixing. Setting GOP and CBP work for me now.
Tested-by: Brandon Brnich <b-brnich@ti.com>
> open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode;
> @@ -1687,7 +1690,7 @@ static int wave5_vpu_open_enc(struct file *filp)
> -6, 6, 1, 0);
> v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
> - 0, 1, 1, 1);
> + 0, 1, 1, 0);
> v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
> V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION,
> 0, 1, 1, 0);
> diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> index dc31689e0d27..7b08fef58217 100644
> --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
> @@ -570,6 +570,7 @@ struct enc_wave_param {
> u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
> u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
> u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
> + u32 constraint_set1_flag: 1; /* enable CBP */
> u32 bg_detection: 1; /* enable background detection */
> };
>
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