The Talos (QCS615) platform includes a QSPI controller used for accessing
external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
the QSPI controller node to enable support for this hardware.
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 75716b4a58d6..fd727924b8ca 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
};
+ qspi_opp_table: opp-table-qspi {
+ compatible = "operating-points-v2";
+
+ opp-60000000 {
+ opp-hz = /bits/ 64 <60000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-133250000 {
+ opp-hz = /bits/ 64 <133250000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-266500000 {
+ opp-hz = /bits/ 64 <266500000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
qup_opp_table: opp-table-qup {
compatible = "operating-points-v2";
@@ -1553,6 +1572,34 @@ tlmm: pinctrl@3100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio44";
+ function = "qspi";
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ qspi_data0123: qspi-data0123-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio49";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ qspi_clk: qspi-clk-state {
+ pins = "gpio48";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio50";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup0";
@@ -3682,6 +3729,39 @@ opp-202000000 {
};
};
+ qspi: spi@88df000 {
+ compatible = "qcom,qcs615-qspi",
+ "qcom,qspi-v1";
+ reg = <0x0 0x088df000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface",
+ "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QSPI QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qspi-config",
+ "qspi-memory";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+
+ iommus = <&apps_smmu 0x160 0x0>;
+
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
dc_noc: interconnect@9160000 {
reg = <0x0 0x09160000 0x0 0x3200>;
compatible = "qcom,qcs615-dc-noc";
--
2.34.1On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
> The Talos (QCS615) platform includes a QSPI controller used for accessing
> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
> the QSPI controller node to enable support for this hardware.
>
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 75716b4a58d6..fd727924b8ca 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>
> };
>
> + qspi_opp_table: opp-table-qspi {
Does device have only one QSPI? Then table goes to device node and
binding needs "opp-table".
Best regards,
Krzysztof
On 3/25/2026 4:43 PM, Krzysztof Kozlowski wrote:
> On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
>> The Talos (QCS615) platform includes a QSPI controller used for accessing
>> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
>> the QSPI controller node to enable support for this hardware.
>>
>> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 80 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>> index 75716b4a58d6..fd727924b8ca 100644
>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>>
>> };
>>
>> + qspi_opp_table: opp-table-qspi {
>
> Does device have only one QSPI? Then table goes to device node and
> binding needs "opp-table".
Yes, it has only one QSPI node. I will add the OPP table inside the node
and include it in the binding as well.
>
> Best regards,
> Krzysztof
>
On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
> The Talos (QCS615) platform includes a QSPI controller used for accessing
> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
> the QSPI controller node to enable support for this hardware.
>
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 75716b4a58d6..fd727924b8ca 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>
> };
>
> + qspi_opp_table: opp-table-qspi {
Why is it not defined inside the QSPI device itself?
> + compatible = "operating-points-v2";
> +
> + opp-60000000 {
> + opp-hz = /bits/ 64 <60000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-133250000 {
> + opp-hz = /bits/ 64 <133250000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-266500000 {
> + opp-hz = /bits/ 64 <266500000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> qup_opp_table: opp-table-qup {
> compatible = "operating-points-v2";
>
--
With best wishes
Dmitry
On 3/24/26 9:51 PM, Dmitry Baryshkov wrote:
> On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
>> The Talos (QCS615) platform includes a QSPI controller used for accessing
>> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
>> the QSPI controller node to enable support for this hardware.
>>
>> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 80 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>> index 75716b4a58d6..fd727924b8ca 100644
>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>>
>> };
>>
>> + qspi_opp_table: opp-table-qspi {
>
> Why is it not defined inside the QSPI device itself?
The QSPI device has #address-cells = <1>, so we'd get:
Warning (spi_bus_reg): /soc@0/spi@88dc000/opp-table-qspi: missing or empty reg property
Konrad
On 3/25/2026 3:02 PM, Konrad Dybcio wrote:
> On 3/24/26 9:51 PM, Dmitry Baryshkov wrote:
>> On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
>>> The Talos (QCS615) platform includes a QSPI controller used for accessing
>>> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
>>> the QSPI controller node to enable support for this hardware.
>>>
>>> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 80 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>>> index 75716b4a58d6..fd727924b8ca 100644
>>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>>> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>>>
>>> };
>>>
>>> + qspi_opp_table: opp-table-qspi {
>>
>> Why is it not defined inside the QSPI device itself?
>
> The QSPI device has #address-cells = <1>, so we'd get:
>
> Warning (spi_bus_reg): /soc@0/spi@88dc000/opp-table-qspi: missing or empty reg property
>
> Konrad
Yes, I am seeing the same warning when the OPP table is placed inline
under the QSPI node.
Given that opp-table nodes are not addressable bus devices and therefore
do not define a reg property, what would be your preferred way to model
this while keeping the DT warning‑free?
Would placing the OPP table as a sibling of the QSPI node (for example
under the same &soc scope) and referencing it via operating-points-v2 be
acceptable in this case, even though there is only a single QSPI instance?
Thanks for your guidance.
Best regards,
Viken
On 3/30/26 1:23 PM, Viken Dadhaniya wrote:
>
>
> On 3/25/2026 3:02 PM, Konrad Dybcio wrote:
>> On 3/24/26 9:51 PM, Dmitry Baryshkov wrote:
>>> On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
>>>> The Talos (QCS615) platform includes a QSPI controller used for accessing
>>>> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
>>>> the QSPI controller node to enable support for this hardware.
>>>>
>>>> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 80 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>>>> index 75716b4a58d6..fd727924b8ca 100644
>>>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>>>> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>>>>
>>>> };
>>>>
>>>> + qspi_opp_table: opp-table-qspi {
>>>
>>> Why is it not defined inside the QSPI device itself?
>>
>> The QSPI device has #address-cells = <1>, so we'd get:
>>
>> Warning (spi_bus_reg): /soc@0/spi@88dc000/opp-table-qspi: missing or empty reg property
>>
>> Konrad
>
> Yes, I am seeing the same warning when the OPP table is placed inline
> under the QSPI node.
>
> Given that opp-table nodes are not addressable bus devices and therefore
> do not define a reg property, what would be your preferred way to model
> this while keeping the DT warning‑free?
>
> Would placing the OPP table as a sibling of the QSPI node (for example
> under the same &soc scope) and referencing it via operating-points-v2 be
> acceptable in this case, even though there is only a single QSPI instance?
I personally don't mind it being in the place where the current version
of the patch puts it, Krzysztof?
Konrad
On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote:
> The Talos (QCS615) platform includes a QSPI controller used for accessing
> external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
> the QSPI controller node to enable support for this hardware.
>
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index 75716b4a58d6..fd727924b8ca 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {
>
> };
>
> + qspi_opp_table: opp-table-qspi {
> + compatible = "operating-points-v2";
> +
> + opp-60000000 {
> + opp-hz = /bits/ 64 <60000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-133250000 {
> + opp-hz = /bits/ 64 <133250000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-266500000 {
> + opp-hz = /bits/ 64 <266500000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> +
> qup_opp_table: opp-table-qup {
> compatible = "operating-points-v2";
>
> @@ -1553,6 +1572,34 @@ tlmm: pinctrl@3100000 {
> #interrupt-cells = <2>;
> wakeup-parent = <&pdc>;
>
> + qspi_cs0: qspi-cs0-state {
> + pins = "gpio44";
> + function = "qspi";
> + bias-disable;
> + drive-strength = <6>;
> + };
> +
> + qspi_data0123: qspi-data0123-state {
> + pins = "gpio45", "gpio46", "gpio47", "gpio49";
> + function = "qspi";
> + bias-pull-down;
> + drive-strength = <6>;
> + };
> +
> + qspi_clk: qspi-clk-state {
> + pins = "gpio48";
> + function = "qspi";
> + bias-pull-down;
> + drive-strength = <6>;
> + };
> +
> + qspi_cs1: qspi-cs1-state {
> + pins = "gpio50";
> + function = "qspi";
> + bias-pull-down;
> + drive-strength = <6>;
> + };
> +
> qup_i2c1_data_clk: qup-i2c1-data-clk-state {
> pins = "gpio4", "gpio5";
> function = "qup0";
> @@ -3682,6 +3729,39 @@ opp-202000000 {
> };
> };
>
> + qspi: spi@88df000 {
> + compatible = "qcom,qcs615-qspi",
> + "qcom,qspi-v1";
> + reg = <0x0 0x088df000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> + <&gcc GCC_QSPI_CORE_CLK>;
> + clock-names = "iface",
> + "core";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QSPI QCOM_ICC_TAG_ALWAYS>,
> + <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
Should those be ACTIVE_ONLY rather than ALWAYS?
> + interconnect-names = "qspi-config",
> + "qspi-memory";
> +
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + operating-points-v2 = <&qspi_opp_table>;
> +
> + iommus = <&apps_smmu 0x160 0x0>;
> +
> + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>;
> + pinctrl-names = "default";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> dc_noc: interconnect@9160000 {
> reg = <0x0 0x09160000 0x0 0x3200>;
> compatible = "qcom,qcs615-dc-noc";
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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