Document the new compatible string "qcom,x1p42100-iris".

The hardware shares the same IP block and binding as SM8550, but is
described by a separate compatible string due to differences in the
clock topology.

In particular, x1p42100 adds an additional clock for the Bitstream
Engine (BSE), which is not present on SM8550. This clock requires
explicit enable/disable handling and frequency configuration, so it
cannot fall back to sm8550.

Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
 .../bindings/media/qcom,sm8550-iris.yaml           | 23 +++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
index 9c4b760508b50251ac467ad44a366689260bfc0d..0400ca1bff05dcef6b742c3fbf77e38adca9f280 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
@@ -26,6 +26,7 @@ properties:
           - qcom,qcs8300-iris
           - qcom,sm8550-iris
           - qcom,sm8650-iris
+          - qcom,x1p42100-iris
 
   reg:
     maxItems: 1
@@ -41,13 +42,16 @@ properties:
       - const: mmcx
 
   clocks:
-    maxItems: 3
+    minItems: 3
+    maxItems: 4
 
   clock-names:
+    minItems: 3
     items:
       - const: iface
       - const: core
       - const: vcodec0_core
+      - const: vcodec0_bse
 
   firmware-name:
     maxItems: 1
@@ -115,6 +119,23 @@ allOf:
           maxItems: 1
         reset-names:
           maxItems: 1
+  - if:
+      properties:
+        compatible:
+          enum:
+            - qcom,x1p42100-iris
+    then:
+      properties:
+        clocks:
+          minItems: 4
+        clock-names:
+          minItems: 4
+    else:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
 
 unevaluatedProperties: false
 

-- 
2.43.0

On Thu, Mar 19, 2026 at 05:23:53PM +0800, Wangao Wang wrote:
> Document the new compatible string "qcom,x1p42100-iris".
> 
> The hardware shares the same IP block and binding as SM8550, but is
> described by a separate compatible string due to differences in the
> clock topology.

It would be described by a separate compatible even if clock topology
was identical, so false implication. Drop the incorrect part and just
describe the hardware.

> 
> In particular, x1p42100 adds an additional clock for the Bitstream
> Engine (BSE), which is not present on SM8550. This clock requires
> explicit enable/disable handling and frequency configuration, so it
> cannot fall back to sm8550.

So same IP block implies devices are compatible, but you say they are
not. How is the BSE clock handled in SM8550 in such case?


Best regards,
Krzysztof