From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the Renesas RZ/V2N PCIe host controller, which is compatible with
the RZ/G3E PCIe IP and therefore uses it as a fallback compatible. The
only difference is that it uses device ID 0x003B.

Make the binding title generic to avoid extending the title for each new
SoC, and update the description to list the supported SoCs and their
capabilities.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 23 ++++++++++++-------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
index a67108c48feb..858ec02e6d62 100644
--- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
@@ -4,21 +4,27 @@
 $id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/G3S PCIe host controller
+title: Renesas RZ/G3S PCIe host controller (and similar SoCs)
 
 maintainers:
   - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
 
-description:
-  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
-  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
-  up to 8 GT/s (Gen3) for RZ/G3E.
+description: |
+  PCIe host controller found in Renesas RZ/G3S and similar SoCs complies
+  with PCIe Base Specification 4.0 and supports different link speeds
+  depending on the SoC variant:
+    - Gen2 (5 GT/s): RZ/G3S
+    - Gen3 (8 GT/s): RZ/G3E, RZ/V2N
 
 properties:
   compatible:
-    enum:
-      - renesas,r9a08g045-pcie # RZ/G3S
-      - renesas,r9a09g047-pcie # RZ/G3E
+    oneOf:
+      - enum:
+          - renesas,r9a08g045-pcie # RZ/G3S
+          - renesas,r9a09g047-pcie # RZ/G3E
+      - items:
+          - const: renesas,r9a09g056-pcie # RZ/V2N
+          - const: renesas,r9a09g047-pcie
 
   reg:
     maxItems: 1
@@ -152,6 +158,7 @@ patternProperties:
         enum:
           - 0x0033
           - 0x0039
+          - 0x003B
 
       clocks:
         items:
-- 
2.53.0

Conventional capitalization for subject lines here is:

  dt-bindings: PCI: renesas,r9a08g045-pcie: Add ...

You can easily see this with:

  git log --oneline --no-merges Documentation/devicetree/bindings/pci/

On Wed, Mar 18, 2026 at 12:44:46PM +0000, Prabhakar wrote:
> ...

> @@ -152,6 +158,7 @@ patternProperties:
>          enum:
>            - 0x0033
>            - 0x0039
> +          - 0x003B

Other constants in this file use lower-case hex.

Hi Bjorn,

Thank you for the review.

On Wed, Mar 18, 2026 at 4:34 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> Conventional capitalization for subject lines here is:
>
>   dt-bindings: PCI: renesas,r9a08g045-pcie: Add ...
>
Ok.

> You can easily see this with:
>
>   git log --oneline --no-merges Documentation/devicetree/bindings/pci/
>
Ok, I will make a note of it.

> On Wed, Mar 18, 2026 at 12:44:46PM +0000, Prabhakar wrote:
> > ...
>
> > @@ -152,6 +158,7 @@ patternProperties:
> >          enum:
> >            - 0x0033
> >            - 0x0039
> > +          - 0x003B
>
> Other constants in this file use lower-case hex.
Agreed, I will switch to lowercase.

Cheers,
Prabhakar