Add video and command mode destination format mappings for RGB101010,
and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate
the new format value.
Make sure this is guarded behind MSM_DSI_6G_VER >= V2.1.0 as anything
older does not support this.
Required for 10 bit panels such as the BOE BF068MWM-TD0.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++
drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++-
4 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index bd3c51c350e7..6a7ea2183a3b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -133,6 +133,7 @@ static const struct msm_dsi_config msm8998_dsi_cfg = {
.io_start = {
{ 0xc994000, 0xc996000 },
},
+ .has_rgb30 = true,
};
static const char * const dsi_sdm660_bus_clk_names[] = {
@@ -152,6 +153,7 @@ static const struct msm_dsi_config sdm660_dsi_cfg = {
.io_start = {
{ 0xc994000, 0xc996000 },
},
+ .has_rgb30 = true,
};
static const char * const dsi_v2_4_clk_names[] = {
@@ -173,6 +175,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
{ 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
{ 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
},
+ .has_rgb30 = true,
};
static const struct regulator_bulk_data sm8550_dsi_regulators[] = {
@@ -188,6 +191,7 @@ static const struct msm_dsi_config sm8550_dsi_cfg = {
.io_start = {
{ 0xae94000, 0xae96000 },
},
+ .has_rgb30 = true,
};
static const struct regulator_bulk_data sm8650_dsi_regulators[] = {
@@ -203,6 +207,7 @@ static const struct msm_dsi_config sm8650_dsi_cfg = {
.io_start = {
{ 0xae94000, 0xae96000 },
},
+ .has_rgb30 = true,
};
static const struct msm_dsi_config kaanapali_dsi_cfg = {
@@ -214,6 +219,7 @@ static const struct msm_dsi_config kaanapali_dsi_cfg = {
.io_start = {
{ 0x9ac0000, 0x9ac3000 },
},
+ .has_rgb30 = true,
};
static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
@@ -230,6 +236,7 @@ static const struct msm_dsi_config sc7280_dsi_cfg = {
.io_start = {
{ 0xae94000, 0xae96000 },
},
+ .has_rgb30 = true,
};
static const struct regulator_bulk_data sa8775p_dsi_regulators[] = {
@@ -246,6 +253,7 @@ static const struct msm_dsi_config sa8775p_dsi_cfg = {
.io_start = {
{ 0xae94000, 0xae96000 },
},
+ .has_rgb30 = true,
};
static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 5dc812028bd5..15cb9b46fadf 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -48,6 +48,7 @@ struct msm_dsi_config {
const char * const *bus_clk_names;
const int num_bus_clks;
const resource_size_t io_start[VARIANTS_MAX][DSI_MAX];
+ bool has_rgb30;
};
struct msm_dsi_host_cfg_ops {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index db6da99375a1..34fd0dc5f7c7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -757,6 +757,7 @@ static inline enum dsi_vid_dst_format
dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
{
switch (mipi_fmt) {
+ case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010;
case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
@@ -769,6 +770,7 @@ static inline enum dsi_cmd_dst_format
dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt)
{
switch (mipi_fmt) {
+ case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010;
case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
case MIPI_DSI_FMT_RGB666_PACKED:
case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
@@ -1698,6 +1700,13 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
if (dsi->lanes > msm_host->num_data_lanes)
return -EINVAL;
+ if (dsi->format == MIPI_DSI_FMT_RGB101010 &&
+ !msm_host->cfg_hnd->cfg->has_rgb30) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev,
+ "RGB101010 not supported on this DSI controller\n");
+ return -EINVAL;
+ }
+
msm_host->channel = dsi->channel;
msm_host->lanes = dsi->lanes;
msm_host->format = dsi->format;
diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
index c7a7b633d747..e40125f75175 100644
--- a/drivers/gpu/drm/msm/registers/display/dsi.xml
+++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
@@ -15,6 +15,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="VID_DST_FORMAT_RGB666" value="1"/>
<value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
<value name="VID_DST_FORMAT_RGB888" value="3"/>
+ <value name="VID_DST_FORMAT_RGB101010" value="4"/>
</enum>
<enum name="dsi_rgb_swap">
<value name="SWAP_RGB" value="0"/>
@@ -39,6 +40,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CMD_DST_FORMAT_RGB565" value="6"/>
<value name="CMD_DST_FORMAT_RGB666" value="7"/>
<value name="CMD_DST_FORMAT_RGB888" value="8"/>
+ <value name="CMD_DST_FORMAT_RGB101010" value="9"/>
</enum>
<enum name="dsi_lane_swap">
<value name="LANE_SWAP_0123" value="0"/>
@@ -142,7 +144,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
</reg32>
<reg32 offset="0x0000c" name="VID_CFG0">
<bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
- <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
+ <!-- high was 5 before DSI 6G 2.1.0 -->
+ <bitfield name="DST_FORMAT" low="4" high="6" type="dsi_vid_dst_format"/>
<bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
<bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
<bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
--
2.53.0On 3/19/26 5:00 AM, Alexander Koskovich wrote:
> Add video and command mode destination format mappings for RGB101010,
> and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate
> the new format value.
>
> Make sure this is guarded behind MSM_DSI_6G_VER >= V2.1.0 as anything
> older does not support this.
>
> Required for 10 bit panels such as the BOE BF068MWM-TD0.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++
> drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++-
> 4 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index bd3c51c350e7..6a7ea2183a3b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -133,6 +133,7 @@ static const struct msm_dsi_config msm8998_dsi_cfg = {
> .io_start = {
> { 0xc994000, 0xc996000 },
> },
> + .has_rgb30 = true,
I wrote a patch to determine this at runtime, and only after I was done, I
noticed that we can already achieve this:
bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
return msm_host->dsc &&
(msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0);
}
let's perhaps extract this to a msm_dsi_host_version_is_gt(u32 major, u32 minor)
or similar
and your assumption about >=v2.1 is corroborated by a doc I have
Konrad
On Thursday, March 19th, 2026 at 5:10 AM, Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
> On 3/19/26 5:00 AM, Alexander Koskovich wrote:
> > Add video and command mode destination format mappings for RGB101010,
> > and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate
> > the new format value.
> >
> > Make sure this is guarded behind MSM_DSI_6G_VER >= V2.1.0 as anything
> > older does not support this.
> >
> > Required for 10 bit panels such as the BOE BF068MWM-TD0.
> >
> > Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++
> > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++
> > drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++-
> > 4 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> > index bd3c51c350e7..6a7ea2183a3b 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> > @@ -133,6 +133,7 @@ static const struct msm_dsi_config msm8998_dsi_cfg = {
> > .io_start = {
> > { 0xc994000, 0xc996000 },
> > },
> > + .has_rgb30 = true,
>
> I wrote a patch to determine this at runtime, and only after I was done, I
> noticed that we can already achieve this:
>
> bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>
> return msm_host->dsc &&
> (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
> msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0);
> }
>
> let's perhaps extract this to a msm_dsi_host_version_is_gt(u32 major, u32 minor)
> or similar
That's what I was looking into initially, but V2_2_0 (0x20000000) is numerically less than V2_1_0 (0x20010000) so didn't think I could do that.
Do you know if msm8998 is correct? Downstream says it is 2.0 not 2.2.
>
> and your assumption about >=v2.1 is corroborated by a doc I have
>
> Konrad
>
Thanks,
Alex
On 3/19/26 10:25 AM, Alexander Koskovich wrote:
> On Thursday, March 19th, 2026 at 5:10 AM, Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
>> On 3/19/26 5:00 AM, Alexander Koskovich wrote:
>>> Add video and command mode destination format mappings for RGB101010,
>>> and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate
>>> the new format value.
>>>
>>> Make sure this is guarded behind MSM_DSI_6G_VER >= V2.1.0 as anything
>>> older does not support this.
>>>
>>> Required for 10 bit panels such as the BOE BF068MWM-TD0.
>>>
>>> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
>>> ---
>>> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++
>>> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
>>> drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++
>>> drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++-
>>> 4 files changed, 22 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>> index bd3c51c350e7..6a7ea2183a3b 100644
>>> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
>>> @@ -133,6 +133,7 @@ static const struct msm_dsi_config msm8998_dsi_cfg = {
>>> .io_start = {
>>> { 0xc994000, 0xc996000 },
>>> },
>>> + .has_rgb30 = true,
>>
>> I wrote a patch to determine this at runtime, and only after I was done, I
>> noticed that we can already achieve this:
>>
>> bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host)
>> {
>> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>>
>> return msm_host->dsc &&
>> (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
>> msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0);
>> }
>>
>> let's perhaps extract this to a msm_dsi_host_version_is_gt(u32 major, u32 minor)
>> or similar
>
> That's what I was looking into initially, but V2_2_0 (0x20000000) is numerically less than V2_1_0 (0x20010000) so didn't think I could do that.
It should be v2.0.0 (0x2(zeroes))
v2.2.0 -> sdm845v1 (unreleased)
v2.2.1 -> sdm670 and sdm845v2
Konrad
On Thu, Mar 19, 2026 at 04:00:05AM +0000, Alexander Koskovich wrote: > Add video and command mode destination format mappings for RGB101010, > and extend the VID_CFG0 DST_FORMAT bitfield to 3 bits to accommodate > the new format value. > > Make sure this is guarded behind MSM_DSI_6G_VER >= V2.1.0 as anything > older does not support this. > > Required for 10 bit panels such as the BOE BF068MWM-TD0. > > Signed-off-by: Alexander Koskovich <akoskovich@pm.me> > --- > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 8 ++++++++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > drivers/gpu/drm/msm/dsi/dsi_host.c | 9 +++++++++ > drivers/gpu/drm/msm/registers/display/dsi.xml | 5 ++++- > 4 files changed, 22 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
© 2016 - 2026 Red Hat, Inc.