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[PATCH 5/8] gpu: nova-core: convert FUSE registers to kernel register macro

Alexandre Courbot posted 8 patches 2 weeks, 5 days ago
There is a newer version of this series
[PATCH 5/8] gpu: nova-core: convert FUSE registers to kernel register macro
Posted by Alexandre Courbot 2 weeks, 5 days ago 
Convert all FUSE registers to use the kernel's register macro and update
the code accordingly.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 drivers/gpu/nova-core/falcon/hal/ga102.rs | 20 +++++++++++------
 drivers/gpu/nova-core/fb/hal/ga100.rs     |  3 ++-
 drivers/gpu/nova-core/fb/hal/tu102.rs     |  3 ++-
 drivers/gpu/nova-core/regs.rs             | 36 ++++++++++++++++++-------------
 4 files changed, 39 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs
index 8f62df10da0a..e3eb6189819f 100644
--- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
@@ -4,7 +4,11 @@
 
 use kernel::{
     device,
-    io::poll::read_poll_timeout,
+    io::{
+        poll::read_poll_timeout,
+        register::Array,
+        Io, //
+    },
     prelude::*,
     time::Delta, //
 };
@@ -60,16 +64,20 @@ fn signature_reg_fuse_version_ga102(
 
     // `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid
     // at build-time.
-    let reg_fuse_version = if engine_id_mask & 0x0001 != 0 {
-        regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx).data()
+    let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 {
+        bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx))
+            .data()
     } else if engine_id_mask & 0x0004 != 0 {
-        regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx).data()
+        bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx))
+            .data()
     } else if engine_id_mask & 0x0400 != 0 {
-        regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).data()
+        bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx))
+            .data()
     } else {
         dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask);
         return Err(EINVAL);
-    };
+    }
+    .into();
 
     // TODO[NUMM]: replace with `last_set_bit` once it lands.
     Ok(u16::BITS - reg_fuse_version.leading_zeros())
diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs
index 629588c75778..1c03783cddef 100644
--- a/drivers/gpu/nova-core/fb/hal/ga100.rs
+++ b/drivers/gpu/nova-core/fb/hal/ga100.rs
@@ -40,7 +40,8 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
 }
 
 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
-    !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
+    !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
+        .display_disabled()
 }
 
 /// Shift applied to the sysmem address before it is written into
diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs
index 515d50872224..281bb796e198 100644
--- a/drivers/gpu/nova-core/fb/hal/tu102.rs
+++ b/drivers/gpu/nova-core/fb/hal/tu102.rs
@@ -29,7 +29,8 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
 }
 
 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
-    !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
+    !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY)
+        .display_disabled()
 }
 
 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 4439464aae4d..9682a94b8b77 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -294,17 +294,19 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
 
 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;
 
-register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT_FPF_SIZE] {
-    15:0    data as u16;
-});
+nv_reg! {
+    NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 {
+        15:0    data;
+    }
 
-register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_FPF_SIZE] {
-    15:0    data as u16;
-});
+    NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 {
+        15:0    data;
+    }
 
-register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0[NV_FUSE_OPT_FPF_SIZE] {
-    15:0    data as u16;
-});
+    NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 {
+        15:0    data;
+    }
+}
 
 // PFALCON
 
@@ -517,15 +519,19 @@ pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) {
 pub(crate) mod gm107 {
     // FUSE
 
-    register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
-        0:0     display_disabled as bool;
-    });
+    nv_reg! {
+        NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
+            0:0     display_disabled => bool;
+        }
+    }
 }
 
 pub(crate) mod ga100 {
     // FUSE
 
-    register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
-        0:0     display_disabled as bool;
-    });
+    nv_reg! {
+        NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
+            0:0     display_disabled => bool;
+        }
+    }
 }

-- 
2.53.0
Re: [PATCH 5/8] gpu: nova-core: convert FUSE registers to kernel register macro
Posted by Eliot Courtney 2 weeks, 4 days ago 
On Wed Mar 18, 2026 at 5:06 PM JST, Alexandre Courbot wrote:
> Convert all FUSE registers to use the kernel's register macro and update
> the code accordingly.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
>  drivers/gpu/nova-core/falcon/hal/ga102.rs | 20 +++++++++++------
>  drivers/gpu/nova-core/fb/hal/ga100.rs     |  3 ++-
>  drivers/gpu/nova-core/fb/hal/tu102.rs     |  3 ++-
>  drivers/gpu/nova-core/regs.rs             | 36 ++++++++++++++++++-------------
>  4 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs
> index 8f62df10da0a..e3eb6189819f 100644
> --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
> +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
> @@ -4,7 +4,11 @@
>  
>  use kernel::{
>      device,
> -    io::poll::read_poll_timeout,
> +    io::{
> +        poll::read_poll_timeout,
> +        register::Array,
> +        Io, //
> +    },
>      prelude::*,
>      time::Delta, //
>  };
> @@ -60,16 +64,20 @@ fn signature_reg_fuse_version_ga102(
>  
>      // `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid
>      // at build-time.
> -    let reg_fuse_version = if engine_id_mask & 0x0001 != 0 {
> -        regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx).data()
> +    let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 {
> +        bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx))
> +            .data()
>      } else if engine_id_mask & 0x0004 != 0 {
> -        regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx).data()
> +        bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx))
> +            .data()
>      } else if engine_id_mask & 0x0400 != 0 {
> -        regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).data()
> +        bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx))
> +            .data()
>      } else {
>          dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask);
>          return Err(EINVAL);
> -    };
> +    }
> +    .into();
>  
>      // TODO[NUMM]: replace with `last_set_bit` once it lands.
>      Ok(u16::BITS - reg_fuse_version.leading_zeros())
> diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs
> index 629588c75778..1c03783cddef 100644
> --- a/drivers/gpu/nova-core/fb/hal/ga100.rs
> +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs
> @@ -40,7 +40,8 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
>  }
>  
>  pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
> -    !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
> +    !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
> +        .display_disabled()
>  }
>  
>  /// Shift applied to the sysmem address before it is written into
> diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs
> index 515d50872224..281bb796e198 100644
> --- a/drivers/gpu/nova-core/fb/hal/tu102.rs
> +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs
> @@ -29,7 +29,8 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
>  }
>  
>  pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
> -    !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
> +    !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY)
> +        .display_disabled()
>  }
>  
>  pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
> index 4439464aae4d..9682a94b8b77 100644
> --- a/drivers/gpu/nova-core/regs.rs
> +++ b/drivers/gpu/nova-core/regs.rs
> @@ -294,17 +294,19 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
>  
>  pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;
>  
> -register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT_FPF_SIZE] {
> -    15:0    data as u16;
> -});
> +nv_reg! {
> +    NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 {
> +        15:0    data;
> +    }
>  
> -register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_FPF_SIZE] {
> -    15:0    data as u16;
> -});
> +    NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 {
> +        15:0    data;
> +    }
>  
> -register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0[NV_FUSE_OPT_FPF_SIZE] {
> -    15:0    data as u16;
> -});
> +    NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 {
> +        15:0    data;
> +    }
> +}

What about using data => u16 here (like below with => bool), then we can
avoid the into()?.

Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>

>  
>  // PFALCON
>  
> @@ -517,15 +519,19 @@ pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) {
>  pub(crate) mod gm107 {
>      // FUSE
>  
> -    register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
> -        0:0     display_disabled as bool;
> -    });
> +    nv_reg! {
> +        NV_FUSE_STATUS_OPT_DISPLAY @ 0x00021c04 {
> +            0:0     display_disabled => bool;
> +        }
> +    }
>  }
>  
>  pub(crate) mod ga100 {
>      // FUSE
>  
> -    register!(NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
> -        0:0     display_disabled as bool;
> -    });
> +    nv_reg! {
> +        NV_FUSE_STATUS_OPT_DISPLAY @ 0x00820c04 {
> +            0:0     display_disabled => bool;
> +        }
> +    }
>  }
Re: [PATCH 5/8] gpu: nova-core: convert FUSE registers to kernel register macro
Posted by Alexandre Courbot 2 weeks, 4 days ago 
On Thu Mar 19, 2026 at 11:17 AM JST, Eliot Courtney wrote:
> On Wed Mar 18, 2026 at 5:06 PM JST, Alexandre Courbot wrote:
>> Convert all FUSE registers to use the kernel's register macro and update
>> the code accordingly.
>>
>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>> ---
>>  drivers/gpu/nova-core/falcon/hal/ga102.rs | 20 +++++++++++------
>>  drivers/gpu/nova-core/fb/hal/ga100.rs     |  3 ++-
>>  drivers/gpu/nova-core/fb/hal/tu102.rs     |  3 ++-
>>  drivers/gpu/nova-core/regs.rs             | 36 ++++++++++++++++++-------------
>>  4 files changed, 39 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs
>> index 8f62df10da0a..e3eb6189819f 100644
>> --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
>> +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
>> @@ -4,7 +4,11 @@
>>  
>>  use kernel::{
>>      device,
>> -    io::poll::read_poll_timeout,
>> +    io::{
>> +        poll::read_poll_timeout,
>> +        register::Array,
>> +        Io, //
>> +    },
>>      prelude::*,
>>      time::Delta, //
>>  };
>> @@ -60,16 +64,20 @@ fn signature_reg_fuse_version_ga102(
>>  
>>      // `ucode_idx` is guaranteed to be in the range [0..15], making the `read` calls provable valid
>>      // at build-time.
>> -    let reg_fuse_version = if engine_id_mask & 0x0001 != 0 {
>> -        regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx).data()
>> +    let reg_fuse_version: u16 = if engine_id_mask & 0x0001 != 0 {
>> +        bar.read(regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::at(ucode_idx))
>> +            .data()
>>      } else if engine_id_mask & 0x0004 != 0 {
>> -        regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx).data()
>> +        bar.read(regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::at(ucode_idx))
>> +            .data()
>>      } else if engine_id_mask & 0x0400 != 0 {
>> -        regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).data()
>> +        bar.read(regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::at(ucode_idx))
>> +            .data()
>>      } else {
>>          dev_err!(dev, "unexpected engine_id_mask {:#x}\n", engine_id_mask);
>>          return Err(EINVAL);
>> -    };
>> +    }
>> +    .into();
>>  
>>      // TODO[NUMM]: replace with `last_set_bit` once it lands.
>>      Ok(u16::BITS - reg_fuse_version.leading_zeros())
>> diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs
>> index 629588c75778..1c03783cddef 100644
>> --- a/drivers/gpu/nova-core/fb/hal/ga100.rs
>> +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs
>> @@ -40,7 +40,8 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
>>  }
>>  
>>  pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
>> -    !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
>> +    !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
>> +        .display_disabled()
>>  }
>>  
>>  /// Shift applied to the sysmem address before it is written into
>> diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs
>> index 515d50872224..281bb796e198 100644
>> --- a/drivers/gpu/nova-core/fb/hal/tu102.rs
>> +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs
>> @@ -29,7 +29,8 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
>>  }
>>  
>>  pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
>> -    !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled()
>> +    !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY)
>> +        .display_disabled()
>>  }
>>  
>>  pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
>> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
>> index 4439464aae4d..9682a94b8b77 100644
>> --- a/drivers/gpu/nova-core/regs.rs
>> +++ b/drivers/gpu/nova-core/regs.rs
>> @@ -294,17 +294,19 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
>>  
>>  pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;
>>  
>> -register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT_FPF_SIZE] {
>> -    15:0    data as u16;
>> -});
>> +nv_reg! {
>> +    NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 {
>> +        15:0    data;
>> +    }
>>  
>> -register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_FPF_SIZE] {
>> -    15:0    data as u16;
>> -});
>> +    NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 {
>> +        15:0    data;
>> +    }
>>  
>> -register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0[NV_FUSE_OPT_FPF_SIZE] {
>> -    15:0    data as u16;
>> -});
>> +    NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 {
>> +        15:0    data;
>> +    }
>> +}
>
> What about using data => u16 here (like below with => bool), then we can
> avoid the into()?.

Of course - I overlooked that, thanks for pointing it out.

Patchew 2.1-devel-ea86937

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