From: Biju Das <biju.das.jz@bp.renesas.com>
Add documentation for the pin controller found on the Renesas RZ/G3L
(R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has
more pins.
Also add header file similar to RZ/G3E and RZ/V2H as it has alpha
numeric ports.
Document renesas,clonech property for controlling clone channel
control register located on SYSC IP block on RZ/G3L SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* Documented renesas,clonech property for controlling clone channel
control register located on SYSC IP block on RZ/G3L SoC.
* Retained the tag as it is similar change for RZ/G3E thermal bindings.
v1->v2:
* Collected tag
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 ++++++++++
.../pinctrl/renesas,r9a08g046-pinctrl.h | 39 +++++++++++++++++++
2 files changed, 59 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 1a94e396b1b0..fb1fe1ea759f 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a08g046-pinctrl # RZ/G3L
- renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g056-pinctrl # RZ/V2N
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
@@ -88,6 +89,16 @@ properties:
- const: main
- const: error
+ renesas,clonech:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to system controller
+ - description: offset of clone channel control register
+ description:
+ Phandle and offset to the system controller containing the clone channel
+ control values.
+
additionalProperties:
anyOf:
- type: object
@@ -150,6 +161,15 @@ additionalProperties:
allOf:
- $ref: pinctrl.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g046-pinctrl
+ then:
+ required:
+ - renesas,clonech
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
new file mode 100644
index 000000000000..660c26477d42
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3L family pinctrl bindings.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */
+#define RZG3L_P2 2
+#define RZG3L_P3 3
+#define RZG3L_P4 4
+#define RZG3L_P5 5
+#define RZG3L_P6 6
+#define RZG3L_P7 7
+#define RZG3L_P8 8
+#define RZG3L_PA 10
+#define RZG3L_PB 11
+#define RZG3L_PC 12
+#define RZG3L_PD 13
+#define RZG3L_PE 14
+#define RZG3L_PF 15
+#define RZG3L_PG 16
+#define RZG3L_PH 17
+#define RZG3L_PJ 19
+#define RZG3L_PK 20
+#define RZG3L_PL 21
+#define RZG3L_PM 22
+#define RZG3L_PS 28
+
+#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f)
+#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */
--
2.43.0