[PATCH v3 0/8] Add Renesas RZ/G3L PINCONTROL support

Biju posted 8 patches 2 weeks, 1 day ago
.../pinctrl/renesas,rzg2l-pinctrl.yaml        |  35 ++
arch/arm64/boot/dts/renesas/r9a07g043.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |   1 +
arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |   1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 514 +++++++++++++++++-
.../pinctrl/renesas,r9a08g046-pinctrl.h       |  39 ++
10 files changed, 588 insertions(+), 7 deletions(-)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
[PATCH v3 0/8] Add Renesas RZ/G3L PINCONTROL support
Posted by Biju 2 weeks, 1 day ago
From: Biju Das <biju.das.jz@bp.renesas.com>

Hi All,

This patch series aims to add basic pin-control support for the Renesas
RZ/G3L SoC. The RZ/G3L pinctrl has an OTHER_POC register compared to other
SoCs for setting the IO domain voltage for AWO, ISO, and WDT.

Document the bindings for the RZ/G3L SoC and add pinctrl definitions in
the driver. Some IPs need to set the register IPCONT_SEL_CLONECH in SYSC
to control the clone channel of the IP. Document the reset-names, as all
SoCs have multiple resets.

v2->v3:
 * Dropped clk, pincontrol device node and pincontrol support for SCIF0
   and GBETH nodes from this series. Will add this later.
 * Documented renesas,clonech property for controlling clone channel
   control register located on SYSC IP block on RZ/G3L SoC.
 * Retained the tag as it is similar change for RZ/G3E thermal bindings.
 * Updated r9a08g046_gpio_configs[] by replacing the typo AWO->ISO.
 * Added PIN_CFG_PUPD to RZG3L_MPXED_ETH_PIN_FUNCS macro
 * Replaced RZG2L_MPXED_COMMON_PIN_FUNCS->RZG3L_MPXED_PIN_FUNCS in 
   RZG3L_MPXED_PIN_FUNCS_POC macro for setting power source for pins.
 * Added clone channel control support in the driver
v1->v2:
 * Split DTSI patches from bindings
 * Fix typo maxItems->minItems in bindings
 * Collected the tag

Biju Das (8):
  dt-bindings: pinctrl: renesas: Document reset-names
  dt-bindings: pinctrl: renesas: Document RZ/G3L SoC
  arm64: dts: renesas: Add reset-names for RZ/G2L and RZ/V2H family SoCs
  pinctrl: renesas: rzg2l: Add support for selecting power source for
    {WDT,AWO,ISO}
  pinctrl: renesas: rzg2l: Add OEN support for RZ/G3L
  pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC
  pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()
  pinctrl: renesas: rzg2l: Add support for clone channel control

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  35 ++
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |   1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 514 +++++++++++++++++-
 .../pinctrl/renesas,r9a08g046-pinctrl.h       |  39 ++
 10 files changed, 588 insertions(+), 7 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h

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2.43.0