Add bindings for Qualcomm Eliza SoC display clock controller (dispcc),
which is very similar to one in SM8750, except new HDMI-related clocks
and additional clock input from HDMI PHY PLL.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/clock/qcom,eliza-dispcc.yaml | 100 +++++++++++++++++
include/dt-bindings/clock/qcom,eliza-dispcc.h | 118 +++++++++++++++++++++
2 files changed, 218 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
new file mode 100644
index 000000000000..174f0ac401ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Display Clock & Reset Controller for Qualcomm Eliza SoC
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
+
+description: |
+ Display clock control module provides the clocks, resets and power
+ domains on Qualcomm Eliza SoC platform.
+
+ See also:
+ - include/dt-bindings/clock/qcom,eliza-dispcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,eliza-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Display's AHB clock
+ - description: sleep clock
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY0
+ - description: VCO DIV clock from DP PHY0
+ - description: Link clock from DP PHY1
+ - description: VCO DIV clock from DP PHY1
+ - description: Link clock from DP PHY2
+ - description: VCO DIV clock from DP PHY2
+ - description: Link clock from DP PHY3
+ - description: VCO DIV clock from DP PHY3
+ - description: HDMI link clock from HDMI PHY
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the MMCX power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing required MMCX performance point.
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
+ #include <dt-bindings/clock/qcom,eliza-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,eliza-dispcc";
+ reg = <0x0af00000 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <&dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&dsi1_phy DSI_PIXEL_PLL_CLK>,
+ <&dp0_phy 0>,
+ <&dp0_phy 1>,
+ <&dp1_phy 0>,
+ <&dp1_phy 1>,
+ <&dp2_phy 0>,
+ <&dp2_phy 1>,
+ <&dp3_phy 0>,
+ <&dp3_phy 1>,
+ <&hdmi_phy>;
+
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,eliza-dispcc.h b/include/dt-bindings/clock/qcom,eliza-dispcc.h
new file mode 100644
index 000000000000..30c6d856fa98
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-dispcc.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0 0
+#define DISP_CC_PLL1 1
+#define DISP_CC_PLL2 2
+#define DISP_CC_ESYNC0_CLK 3
+#define DISP_CC_ESYNC0_CLK_SRC 4
+#define DISP_CC_ESYNC1_CLK 5
+#define DISP_CC_ESYNC1_CLK_SRC 6
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK 7
+#define DISP_CC_MDSS_AHB1_CLK 8
+#define DISP_CC_MDSS_AHB_CLK 9
+#define DISP_CC_MDSS_AHB_CLK_SRC 10
+#define DISP_CC_MDSS_BYTE0_CLK 11
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 12
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 13
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 14
+#define DISP_CC_MDSS_BYTE1_CLK 15
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 16
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 17
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 18
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 19
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 20
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 21
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 22
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 23
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 24
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 25
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 26
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 27
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 28
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 29
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 30
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 31
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 32
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 33
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 34
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 35
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 36
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 38
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 40
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 41
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 43
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 44
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 45
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 46
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 47
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 48
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 54
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 55
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 57
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 60
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 61
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 62
+#define DISP_CC_MDSS_ESC0_CLK 63
+#define DISP_CC_MDSS_ESC0_CLK_SRC 64
+#define DISP_CC_MDSS_ESC1_CLK 65
+#define DISP_CC_MDSS_ESC1_CLK_SRC 66
+#define DISP_CC_MDSS_HDMI_AHBM_CLK 67
+#define DISP_CC_MDSS_HDMI_APP_CLK 68
+#define DISP_CC_MDSS_HDMI_APP_CLK_SRC 69
+#define DISP_CC_MDSS_HDMI_CRYPTO_CLK 70
+#define DISP_CC_MDSS_HDMI_INTF_CLK 71
+#define DISP_CC_MDSS_HDMI_PCLK_CLK 72
+#define DISP_CC_MDSS_HDMI_PCLK_CLK_SRC 73
+#define DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC 74
+#define DISP_CC_MDSS_MDP1_CLK 75
+#define DISP_CC_MDSS_MDP_CLK 76
+#define DISP_CC_MDSS_MDP_CLK_SRC 77
+#define DISP_CC_MDSS_MDP_LUT1_CLK 78
+#define DISP_CC_MDSS_MDP_LUT_CLK 79
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 80
+#define DISP_CC_MDSS_PCLK0_CLK 81
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 82
+#define DISP_CC_MDSS_PCLK1_CLK 83
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 84
+#define DISP_CC_MDSS_PCLK2_CLK 85
+#define DISP_CC_MDSS_PCLK2_CLK_SRC 86
+#define DISP_CC_MDSS_RSCC_AHB_CLK 87
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 88
+#define DISP_CC_MDSS_VSYNC1_CLK 89
+#define DISP_CC_MDSS_VSYNC_CLK 90
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 91
+#define DISP_CC_OSC_CLK 92
+#define DISP_CC_OSC_CLK_SRC 93
+#define DISP_CC_SLEEP_CLK 94
+#define DISP_CC_SLEEP_CLK_SRC 95
+#define DISP_CC_XO_CLK 96
+#define DISP_CC_XO_CLK_SRC 97
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_CORE_INT2_BCR 1
+#define DISP_CC_MDSS_RSCC_BCR 2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+#define MDSS_INT2_GDSC 1
+
+#endif
--
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