From: Nick Hawkins <nick.hawkins@hpe.com>

The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant
servers.  Its eMMC controller is based on the DesignWare Cores MSHC IP
(snps,dwcmshc) but requires a small set of platform-specific quirks
that cannot be expressed through the existing generic dwcmshc code
paths.

This series adds support for the 'hpe,gsc-dwcmshc' compatible:

Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the
new compatible and the mandatory 'hpe,gxp-sysreg' syscon phandle
(with register offset argument) for MSHCCS register access.  The HPE
GSC exposes only a single 'core' clock, so the clocks/clock-names
properties are constrained to a single item for this compatible.

Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c:

  * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to
    a clock mux on the GSC SoC, not a divider.  When running at
    200 MHz (HS200) freq_sel must be forced to 1 to select the correct
    high-frequency source.

  * dwcmshc_hpe_vendor_specific(): disables the command-conflict check
    and programs ATCTRL using existing AT_CTRL_* macros for reliable
    HS200 signal integrity on the GSC board topology.

  * dwcmshc_hpe_set_emmc(): helper that unconditionally sets
    DWCMSHC_CARD_IS_EMMC.  Called from both the reset and
    UHS-signaling paths.

  * dwcmshc_hpe_reset(): calls dwcmshc_reset(), re-applies vendor
    config, and calls dwcmshc_hpe_set_emmc().  The controller clears
    this bit on every reset; leaving it clear causes card-detect
    misidentification on the eMMC-only slot.

  * dwcmshc_hpe_set_uhs_signaling(): wraps dwcmshc_set_uhs_signaling()
    and calls dwcmshc_hpe_set_emmc() for all timing modes.

  * dwcmshc_hpe_gsc_init(): obtains the SoC register block and MSHCCS
    offset via the 'hpe,gxp-sysreg' syscon phandle argument and sets
    SCGSyncDis (BIT(18)) in MSHCCS to allow the HS200 RX delay lines
    to settle while the card clock is stopped.  Enables SDHCI v4 mode.

  * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
    (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN
    (preset-value registers not populated in GSC ROM).

All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF
match entry.  No existing platform (Rockchip, T-Head, sg2042, Sophgo,
etc.) has any code path change.

Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately
as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/).

Changes since v3:
  - dt-binding: Changed 'hpe,gxp-sysreg' from a bare phandle to a
    phandle-array with register offset argument, as suggested by
    Krzysztof Kozlowski.
  - dt-binding: Added else clause to disallow 'hpe,gxp-sysreg' for
    non-HPE compatibles, as suggested by Krzysztof Kozlowski.
  - dt-binding: Dropped the third example node; two are sufficient,
    as noted by Krzysztof Kozlowski.
  - Driver: Fixed multi-line comment to use the standard block comment
    style used in this file (opening '/*' on its own line), as noted
    by Adrian Hunter.
  - Driver: Added DWCMSHC_HOST_CTRL3_CMD_CONFLICT define for the
    previously bare BIT(0), as suggested by Adrian Hunter.
  - Driver: Extracted the CARD_IS_EMMC read-modify-write into a
    dwcmshc_hpe_set_emmc() helper, called from both
    dwcmshc_hpe_reset() and dwcmshc_hpe_set_uhs_signaling(), as
    suggested by Adrian Hunter.
  - Driver: Fixed regmap_update_bits() argument alignment, as noted
    by Adrian Hunter.
  - Driver: Moved HPE_GSC_MSHCCS_SCGSYNCDIS macro to the top-level
    defines section, as suggested by Shawn Lin.
  - Driver: Switched from syscon_regmap_lookup_by_phandle() with
    hardcoded offset to syscon_regmap_lookup_by_phandle_args() to
    read the MSHCCS offset from the DT phandle argument.

Changes since v2:
  - Replaced raw ATCTRL magic value 0x021f0005 with existing AT_CTRL_*
    macros and FIELD_PREP(), as suggested by Shawn Lin.
  - Refactored dwcmshc_hpe_set_uhs_signaling() to wrap
    dwcmshc_set_uhs_signaling() instead of duplicating the body,
    as suggested by Shawn Lin.
  - Dropped redundant 'maxItems: 1' from clocks and clock-names in the
    dt-binding conditional block; the items list already implies the
    count (reported by dt-review-ci / dtschema).

Changes since v1:
  - Replaced the second reg entry for MSHCCS with an 'hpe,gxp-sysreg'
    syscon phandle + regmap access, as suggested by Conor Dooley.
  - Driver now uses syscon_regmap_lookup_by_phandle() and
    regmap_update_bits() instead of devm_platform_ioremap_resource().

Nick Hawkins (2):
  dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
  mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support

 .../bindings/mmc/snps,dwcmshc-sdhci.yaml      |  32 ++++
 drivers/mmc/host/sdhci-of-dwcmshc.c           | 147 ++++++++++++++++++
 2 files changed, 179 insertions(+)

-- 
2.34.1

On Mon, 16 Mar 2026 at 16:01, <nick.hawkins@hpe.com> wrote:
>
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> The HPE GSC is an ARM64 (Cortex-A53) BMC SoC used on HPE ProLiant
> servers.  Its eMMC controller is based on the DesignWare Cores MSHC IP
> (snps,dwcmshc) but requires a small set of platform-specific quirks
> that cannot be expressed through the existing generic dwcmshc code
> paths.
>
> This series adds support for the 'hpe,gsc-dwcmshc' compatible:
>
> Patch 1 extends the snps,dwcmshc-sdhci.yaml binding to document the
> new compatible and the mandatory 'hpe,gxp-sysreg' syscon phandle
> (with register offset argument) for MSHCCS register access.  The HPE
> GSC exposes only a single 'core' clock, so the clocks/clock-names
> properties are constrained to a single item for this compatible.
>
> Patch 2 adds the HPE-specific driver code in sdhci-of-dwcmshc.c:
>
>   * dwcmshc_hpe_set_clock(): SDHCI_CLOCK_CONTROL.freq_sel is wired to
>     a clock mux on the GSC SoC, not a divider.  When running at
>     200 MHz (HS200) freq_sel must be forced to 1 to select the correct
>     high-frequency source.
>
>   * dwcmshc_hpe_vendor_specific(): disables the command-conflict check
>     and programs ATCTRL using existing AT_CTRL_* macros for reliable
>     HS200 signal integrity on the GSC board topology.
>
>   * dwcmshc_hpe_set_emmc(): helper that unconditionally sets
>     DWCMSHC_CARD_IS_EMMC.  Called from both the reset and
>     UHS-signaling paths.
>
>   * dwcmshc_hpe_reset(): calls dwcmshc_reset(), re-applies vendor
>     config, and calls dwcmshc_hpe_set_emmc().  The controller clears
>     this bit on every reset; leaving it clear causes card-detect
>     misidentification on the eMMC-only slot.
>
>   * dwcmshc_hpe_set_uhs_signaling(): wraps dwcmshc_set_uhs_signaling()
>     and calls dwcmshc_hpe_set_emmc() for all timing modes.
>
>   * dwcmshc_hpe_gsc_init(): obtains the SoC register block and MSHCCS
>     offset via the 'hpe,gxp-sysreg' syscon phandle argument and sets
>     SCGSyncDis (BIT(18)) in MSHCCS to allow the HS200 RX delay lines
>     to settle while the card clock is stopped.  Enables SDHCI v4 mode.
>
>   * sdhci_dwcmshc_hpe_gsc_pdata sets SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
>     (base clock not in capabilities) and SDHCI_QUIRK2_PRESET_VALUE_BROKEN
>     (preset-value registers not populated in GSC ROM).
>
> All new symbols are exclusively selected by the 'hpe,gsc-dwcmshc' OF
> match entry.  No existing platform (Rockchip, T-Head, sg2042, Sophgo,
> etc.) has any code path change.
>
> Note: the DTS node for 'hpe,gsc-dwcmshc' will be submitted separately
> as part of the HPE GSC base platform series (arch/arm64/boot/dts/hpe/).
>
> Changes since v3:
>   - dt-binding: Changed 'hpe,gxp-sysreg' from a bare phandle to a
>     phandle-array with register offset argument, as suggested by
>     Krzysztof Kozlowski.
>   - dt-binding: Added else clause to disallow 'hpe,gxp-sysreg' for
>     non-HPE compatibles, as suggested by Krzysztof Kozlowski.
>   - dt-binding: Dropped the third example node; two are sufficient,
>     as noted by Krzysztof Kozlowski.
>   - Driver: Fixed multi-line comment to use the standard block comment
>     style used in this file (opening '/*' on its own line), as noted
>     by Adrian Hunter.
>   - Driver: Added DWCMSHC_HOST_CTRL3_CMD_CONFLICT define for the
>     previously bare BIT(0), as suggested by Adrian Hunter.
>   - Driver: Extracted the CARD_IS_EMMC read-modify-write into a
>     dwcmshc_hpe_set_emmc() helper, called from both
>     dwcmshc_hpe_reset() and dwcmshc_hpe_set_uhs_signaling(), as
>     suggested by Adrian Hunter.
>   - Driver: Fixed regmap_update_bits() argument alignment, as noted
>     by Adrian Hunter.
>   - Driver: Moved HPE_GSC_MSHCCS_SCGSYNCDIS macro to the top-level
>     defines section, as suggested by Shawn Lin.
>   - Driver: Switched from syscon_regmap_lookup_by_phandle() with
>     hardcoded offset to syscon_regmap_lookup_by_phandle_args() to
>     read the MSHCCS offset from the DT phandle argument.
>
> Changes since v2:
>   - Replaced raw ATCTRL magic value 0x021f0005 with existing AT_CTRL_*
>     macros and FIELD_PREP(), as suggested by Shawn Lin.
>   - Refactored dwcmshc_hpe_set_uhs_signaling() to wrap
>     dwcmshc_set_uhs_signaling() instead of duplicating the body,
>     as suggested by Shawn Lin.
>   - Dropped redundant 'maxItems: 1' from clocks and clock-names in the
>     dt-binding conditional block; the items list already implies the
>     count (reported by dt-review-ci / dtschema).
>
> Changes since v1:
>   - Replaced the second reg entry for MSHCCS with an 'hpe,gxp-sysreg'
>     syscon phandle + regmap access, as suggested by Conor Dooley.
>   - Driver now uses syscon_regmap_lookup_by_phandle() and
>     regmap_update_bits() instead of devm_platform_ioremap_resource().
>
> Nick Hawkins (2):
>   dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
>   mmc: sdhci-of-dwcmshc: Add HPE GSC eMMC support
>
>  .../bindings/mmc/snps,dwcmshc-sdhci.yaml      |  32 ++++
>  drivers/mmc/host/sdhci-of-dwcmshc.c           | 147 ++++++++++++++++++
>  2 files changed, 179 insertions(+)
>
> --
> 2.34.1
>

The series applied for next, thanks!

Note that, I amended patch2 according to Adrian's comment.

Kind regards
Uffe