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[PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller

Viken Dadhaniya posted 3 patches 3 weeks ago
There is a newer version of this series
[PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
Posted by Viken Dadhaniya 3 weeks ago 
Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
The controller is connected via SPI3 and uses a 40 MHz oscillator.

The setup was tested with CAN-FD loopback and actual data transfer
using an external PCAN-USB FD adapter.

Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
v1 -> v2:

- Drop the gpio-hog property.
- Add the microchip,xstbyen property to enable transceiver standby control.

v1 Link: https://lore.kernel.org/all/20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com/
---
---
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae..245961722f84 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -44,6 +44,14 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
+	clocks {
+		mcp2518fd_osc: can-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <40000000>;
+			#clock-cells = <0>;
+		};
+	};
+
 	dp-connector {
 		compatible = "dp-connector";
 		label = "DP";
@@ -1151,6 +1159,20 @@ platform {
 	};
 };
 
+&spi3 {
+	status = "okay";
+
+	can@0 {
+		compatible = "microchip,mcp2518fd";
+		reg = <0>;
+		interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&mcp2518fd_osc>;
+		spi-max-frequency = <10000000>;
+		vdd-supply = <&vreg_l11c_2p8>;
+		microchip,xstbyen;
+	};
+};
+
 &swr2 {
 	status = "okay";
 
-- 
2.34.1
Re: [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
Posted by Konrad Dybcio 2 weeks, 5 days ago 
On 3/16/26 2:19 PM, Viken Dadhaniya wrote:
> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
> The controller is connected via SPI3 and uses a 40 MHz oscillator.
> 
> The setup was tested with CAN-FD loopback and actual data transfer
> using an external PCAN-USB FD adapter.
> 
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad
Re: [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
Posted by Marc Kleine-Budde 3 weeks ago 
On 16.03.2026 18:49:50, Viken Dadhaniya wrote:
> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
> The controller is connected via SPI3 and uses a 40 MHz oscillator.
>
> The setup was tested with CAN-FD loopback and actual data transfer
> using an external PCAN-USB FD adapter.

IIRC a board DT update should go independent of the driver update.

> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---
> v1 -> v2:
>
> - Drop the gpio-hog property.
> - Add the microchip,xstbyen property to enable transceiver standby control.
>
> v1 Link: https://lore.kernel.org/all/20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com/
> ---
> ---
>  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index e3d2f01881ae..245961722f84 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -44,6 +44,14 @@ chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
>
> +	clocks {
> +		mcp2518fd_osc: can-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <40000000>;
> +			#clock-cells = <0>;
> +		};
> +	};
> +
>  	dp-connector {
>  		compatible = "dp-connector";
>  		label = "DP";
> @@ -1151,6 +1159,20 @@ platform {
>  	};
>  };
>
> +&spi3 {
> +	status = "okay";
> +
> +	can@0 {
> +		compatible = "microchip,mcp2518fd";
> +		reg = <0>;
> +		interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&mcp2518fd_osc>;
> +		spi-max-frequency = <10000000>;

Why do you limit the frequency to 10 MHz? Is this a HW limitation?

With a 40 MHz clock the chip supports up to 17 MHz (not 20 MHz due to
the erratum).

Marc

-- 
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Re: [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
Posted by Viken Dadhaniya 2 weeks, 3 days ago 

On 3/16/2026 6:59 PM, Marc Kleine-Budde wrote:
> On 16.03.2026 18:49:50, Viken Dadhaniya wrote:
>> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
>> The controller is connected via SPI3 and uses a 40 MHz oscillator.
>>
>> The setup was tested with CAN-FD loopback and actual data transfer
>> using an external PCAN-USB FD adapter.
> 
> IIRC a board DT update should go independent of the driver update.

Sure, I will send the device tree changes separately.

> 
>> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
>> ---
>> v1 -> v2:
>>
>> - Drop the gpio-hog property.
>> - Add the microchip,xstbyen property to enable transceiver standby control.
>>
>> v1 Link: https://lore.kernel.org/all/20260108125200.2803112-3-viken.dadhaniya@oss.qualcomm.com/
>> ---
>> ---
>>  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> index e3d2f01881ae..245961722f84 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> @@ -44,6 +44,14 @@ chosen {
>>  		stdout-path = "serial0:115200n8";
>>  	};
>>
>> +	clocks {
>> +		mcp2518fd_osc: can-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <40000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>>  	dp-connector {
>>  		compatible = "dp-connector";
>>  		label = "DP";
>> @@ -1151,6 +1159,20 @@ platform {
>>  	};
>>  };
>>
>> +&spi3 {
>> +	status = "okay";
>> +
>> +	can@0 {
>> +		compatible = "microchip,mcp2518fd";
>> +		reg = <0>;
>> +		interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>;
>> +		clocks = <&mcp2518fd_osc>;
>> +		spi-max-frequency = <10000000>;
> 
> Why do you limit the frequency to 10 MHz? Is this a HW limitation?
> 
> With a 40 MHz clock the chip supports up to 17 MHz (not 20 MHz due to
> the erratum).

The 10 MHz was overly conservative. Testing on this board shows:

  spi-max-frequency = <14000000>: actual SCK = 12.8 MHz  => OK
  spi-max-frequency = <15000000>: actual SCK = 15.0 MHz  => FAIL

Any SCK >= 14.7 MHz fails to initialize the MCP251xFD on this board,
so 12.8 MHz is the highest reliable SCK within the erratum limit of
17 MHz.

Will update to spi-max-frequency = <14000000>.

> 
> Marc
>

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