The buffer pool is a quantity of memory available for buffering a group
of flows (e.g. frames having the same priority, frames received from the
same port), while waiting to be transmitted on a port. The buffer pool
tracks internal memory consumption with upper bound limits and optionally
a non-shared portion when associated with a shared buffer pool. Currently
the shared buffer pool is not supported, it will be added in the future.
For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is
allocated two buffer pools. For frames with priorities of 0 to 3, they
will be mapped to the first buffer pool; For frames with priorities of
4 to 7, they will be mapped to the second buffer pool. Each buffer pool
has a flow control on threshold and a flow control off threshold. By
setting these threshold, add the flow control support to each port.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
drivers/net/dsa/netc/netc_main.c | 130 ++++++++++++++++++++++++++
drivers/net/dsa/netc/netc_switch.h | 9 ++
drivers/net/dsa/netc/netc_switch_hw.h | 12 +++
3 files changed, 151 insertions(+)
diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
index fd952b507cbd..15dd8d89f66d 100644
--- a/drivers/net/dsa/netc/netc_main.c
+++ b/drivers/net/dsa/netc/netc_main.c
@@ -402,6 +402,8 @@ static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo)
static void netc_port_fixed_config(struct netc_port *np)
{
+ u32 pqnt = 0xffff, qth = 0xff00;
+
/* Default IPV and DR setting */
netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE,
PQOSMR_VS | PQOSMR_VE);
@@ -409,6 +411,15 @@ static void netc_port_fixed_config(struct netc_port *np)
/* Enable L2 and L3 DOS */
netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE,
PCR_L2DOSE | PCR_L3DOSE);
+
+ /* Set the quanta value of TX PAUSE frame */
+ netc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), pqnt);
+
+ /* When a quanta timer counts down and reaches this value,
+ * the MAC sends a refresh PAUSE frame with the programmed
+ * full quanta value if a pause condition still exists.
+ */
+ netc_mac_port_wr(np, NETC_PM_PAUSE_TRHESH(0), qth);
}
static void netc_port_default_config(struct netc_port *np)
@@ -640,6 +651,77 @@ static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv)
bcast, NETC_STANDALONE_PVID);
}
+static u32 netc_get_buffer_pool_num(struct netc_switch *priv)
+{
+ return netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP;
+}
+
+static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping)
+{
+ u32 pbpmcr0 = lower_32_bits(mapping);
+ u32 pbpmcr1 = upper_32_bits(mapping);
+
+ netc_port_wr(np, NETC_PBPMCR0, pbpmcr0);
+ netc_port_wr(np, NETC_PBPMCR1, pbpmcr1);
+}
+
+static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv)
+{
+ int num_port_bp = priv->num_bp / priv->info->num_ports;
+ int q = NETC_IPV_NUM / num_port_bp;
+ int r = NETC_IPV_NUM % num_port_bp;
+ int num = q + r;
+
+ /* IPV-to–buffer-pool mapping per port:
+ * Each port is allocated `num_port_bp` buffer pools and supports 8
+ * IPVs, where a higher IPV indicates a higher frame priority. Each
+ * IPV can be mapped to only one buffer pool.
+ *
+ * The mapping rule is as follows:
+ * - The first `num` IPVs share the port’s first buffer pool (index
+ * `base_id`).
+ * - After that, every `q` IPVs share one buffer pool, with pool
+ * indices increasing sequentially.
+ */
+ for (int i = 0; i < priv->info->num_ports; i++) {
+ u32 base_id = i * num_port_bp;
+ u32 bp_id = base_id;
+ u64 mapping = 0;
+
+ for (int ipv = 0; ipv < NETC_IPV_NUM; ipv++) {
+ /* Update the buffer pool index */
+ if (ipv >= num)
+ bp_id = base_id + ((ipv - num) / q) + 1;
+
+ mapping |= (u64)bp_id << (ipv * 8);
+ }
+
+ netc_port_set_pbpmcr(priv->ports[i], mapping);
+ }
+}
+
+static int netc_switch_bpt_default_config(struct netc_switch *priv)
+{
+ priv->num_bp = netc_get_buffer_pool_num(priv);
+ priv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp,
+ sizeof(struct bpt_cfge_data),
+ GFP_KERNEL);
+ if (!priv->bpt_list)
+ return -ENOMEM;
+
+ /* Initialize the maximum threshold of each buffer pool entry */
+ for (int i = 0; i < priv->num_bp; i++) {
+ struct bpt_cfge_data *cfge = &priv->bpt_list[i];
+
+ cfge->max_thresh = cpu_to_le16(NETC_BP_THRESH);
+ ntmp_bpt_update_entry(&priv->ntmp, i, cfge);
+ }
+
+ netc_ipv_to_buffer_pool_mapping(priv);
+
+ return 0;
+}
+
static int netc_setup(struct dsa_switch *ds)
{
struct netc_switch *priv = ds->priv;
@@ -667,6 +749,10 @@ static int netc_setup(struct dsa_switch *ds)
dsa_switch_for_each_available_port(dp, ds)
netc_port_default_config(priv->ports[dp->index]);
+ err = netc_switch_bpt_default_config(priv);
+ if (err)
+ goto free_ntmp_user;
+
err = netc_add_standalone_vlan_entry(priv);
if (err)
goto free_ntmp_user;
@@ -1241,6 +1327,40 @@ static void netc_port_set_hd_flow_control(struct netc_port *np, bool en)
en ? PM_CMD_CFG_HD_FCEN : 0);
}
+static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause)
+{
+ struct netc_switch *priv = np->switch_priv;
+ int port = np->dp->index;
+ int i, j, num_bp;
+
+ num_bp = priv->num_bp / priv->info->num_ports;
+ for (i = 0, j = port * num_bp; i < num_bp; i++, j++) {
+ struct bpt_cfge_data *cfge;
+
+ cfge = &priv->bpt_list[j];
+ if (tx_pause) {
+ cfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON);
+ cfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF);
+ cfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG,
+ BPT_FC_CFG_EN_BPFC);
+ cfge->fc_ports = cpu_to_le32(BIT(port));
+ } else {
+ cfge->fc_on_thresh = cpu_to_le16(0);
+ cfge->fc_off_thresh = cpu_to_le16(0);
+ cfge->fccfg_sbpen = 0;
+ cfge->fc_ports = cpu_to_le32(0);
+ }
+
+ ntmp_bpt_update_entry(&priv->ntmp, j, cfge);
+ }
+}
+
+static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause)
+{
+ netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN,
+ rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN);
+}
+
static void netc_port_mac_rx_enable(struct netc_port *np)
{
netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0);
@@ -1305,7 +1425,17 @@ static void netc_mac_link_up(struct phylink_config *config,
net_port_set_rmii_mii_mac(np, speed, duplex);
}
+ if (duplex == DUPLEX_HALF) {
+ /* As per 802.3 annex 31B, PAUSE frames are only supported
+ * when the link is configured for full duplex operation.
+ */
+ tx_pause = false;
+ rx_pause = false;
+ }
+
netc_port_set_hd_flow_control(np, duplex == DUPLEX_HALF);
+ netc_port_set_tx_pause(np, tx_pause);
+ netc_port_set_rx_pause(np, rx_pause);
netc_port_mac_rx_enable(np);
}
diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h
index 4b229a71578e..7ebffb136b2f 100644
--- a/drivers/net/dsa/netc/netc_switch.h
+++ b/drivers/net/dsa/netc/netc_switch.h
@@ -32,6 +32,12 @@
#define NETC_STANDALONE_PVID 0
+#define NETC_IPV_NUM 8
+/* MANT = bits 11:4, EXP = bits 3:0, threshold = MANT * 2 ^ EXP */
+#define NETC_BP_THRESH 0x334
+#define NETC_FC_THRESH_ON 0x533
+#define NETC_FC_THRESH_OFF 0x3c3
+
struct netc_switch;
struct netc_switch_info {
@@ -90,6 +96,9 @@ struct netc_switch {
struct ntmp_user ntmp;
struct hlist_head fdb_list;
struct mutex fdbt_lock; /* FDB table lock */
+
+ u32 num_bp;
+ struct bpt_cfge_data *bpt_list;
};
#define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv))
diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h
index a2b0c1a712f8..7ef870fbba4d 100644
--- a/drivers/net/dsa/netc/netc_switch_hw.h
+++ b/drivers/net/dsa/netc/netc_switch_hw.h
@@ -12,6 +12,12 @@
#define NETC_SWITCH_DEVICE_ID 0xeef2
/* Definition of Switch base registers */
+#define NETC_BPCAPR 0x0008
+#define BPCAPR_NUM_BP GENMASK(7, 0)
+
+#define NETC_PBPMCR0 0x0400
+#define NETC_PBPMCR1 0x0404
+
#define NETC_CBDRMR(a) (0x0800 + (a) * 0x30)
#define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30)
#define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30)
@@ -163,6 +169,12 @@ enum netc_stg_stage {
#define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400)
#define PM_IEVENT_RX_EMPTY BIT(6)
+#define NETC_PM_PAUSE_QUANTA(a) (0x1054 + (a) * 0x400)
+#define PAUSE_QUANTA_PQNT GENMASK(15, 0)
+
+#define NETC_PM_PAUSE_TRHESH(a) (0x1064 + (a) * 0x400)
+#define PAUSE_TRHESH_QTH GENMASK(15, 0)
+
#define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400)
#define PM_IF_MODE_IFMODE GENMASK(2, 0)
#define IFMODE_MII 1
--
2.34.1
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: dsa: netc: initialize buffer bool table and implement flow-control
The buffer pool is a quantity of memory available for buffering a group
of flows (e.g. frames having the same priority, frames received from the
same port), while waiting to be transmitted on a port. The buffer pool
tracks internal memory consumption with upper bound limits and optionally
a non-shared portion when associated with a shared buffer pool. Currently
the shared buffer pool is not supported, it will be added in the future.
For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is
allocated two buffer pools. For frames with priorities of 0 to 3, they
will be mapped to the first buffer pool; For frames with priorities of
4 to 7, they will be mapped to the second buffer pool. Each buffer pool
has a flow control on threshold and a flow control off threshold. By
setting these threshold, add the flow control support to each port.
> diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c
> index fd952b507cbd..15dd8d89f66d 100644
> --- a/drivers/net/dsa/netc/netc_main.c
> +++ b/drivers/net/dsa/netc/netc_main.c
[ ... ]
> @@ -640,6 +651,77 @@ static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv)
> bcast, NETC_STANDALONE_PVID);
> }
>
> +static u32 netc_get_buffer_pool_num(struct netc_switch *priv)
> +{
> + return netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP;
> +}
> +
> +static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping)
> +{
> + u32 pbpmcr0 = lower_32_bits(mapping);
> + u32 pbpmcr1 = upper_32_bits(mapping);
> +
> + netc_port_wr(np, NETC_PBPMCR0, pbpmcr0);
> + netc_port_wr(np, NETC_PBPMCR1, pbpmcr1);
> +}
> +
> +static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv)
> +{
> + int num_port_bp = priv->num_bp / priv->info->num_ports;
> + int q = NETC_IPV_NUM / num_port_bp;
> + int r = NETC_IPV_NUM % num_port_bp;
> + int num = q + r;
> +
> + /* IPV-to–buffer-pool mapping per port:
> + * Each port is allocated `num_port_bp` buffer pools and supports 8
> + * IPVs, where a higher IPV indicates a higher frame priority. Each
> + * IPV can be mapped to only one buffer pool.
> + *
> + * The mapping rule is as follows:
> + * - The first `num` IPVs share the port's first buffer pool (index
> + * `base_id`).
> + * - After that, every `q` IPVs share one buffer pool, with pool
> + * indices increasing sequentially.
> + */
> + for (int i = 0; i < priv->info->num_ports; i++) {
> + u32 base_id = i * num_port_bp;
> + u32 bp_id = base_id;
> + u64 mapping = 0;
> +
> + for (int ipv = 0; ipv < NETC_IPV_NUM; ipv++) {
> + /* Update the buffer pool index */
> + if (ipv >= num)
> + bp_id = base_id + ((ipv - num) / q) + 1;
> +
> + mapping |= (u64)bp_id << (ipv * 8);
> + }
> +
> + netc_port_set_pbpmcr(priv->ports[i], mapping);
> + }
> +}
> +
> +static int netc_switch_bpt_default_config(struct netc_switch *priv)
> +{
> + priv->num_bp = netc_get_buffer_pool_num(priv);
> + priv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp,
> + sizeof(struct bpt_cfge_data),
> + GFP_KERNEL);
> + if (!priv->bpt_list)
> + return -ENOMEM;
> +
> + /* Initialize the maximum threshold of each buffer pool entry */
> + for (int i = 0; i < priv->num_bp; i++) {
> + struct bpt_cfge_data *cfge = &priv->bpt_list[i];
> +
> + cfge->max_thresh = cpu_to_le16(NETC_BP_THRESH);
> + ntmp_bpt_update_entry(&priv->ntmp, i, cfge);
> + }
Is the return value of ntmp_bpt_update_entry() checked here? Other NTMP
table operations in this driver propagate errors from the update functions.
Looking at ntmp_fdbt_update_entry() usage in netc_port_set_fdb_entry():
drivers/net/dsa/netc/netc_main.c:netc_port_set_fdb_entry() {
...
err = ntmp_fdbt_update_entry(&priv->ntmp, fdbt, &hdr);
if (err)
return err;
}
And ntmp_vft_add_entry() usage in netc_add_standalone_vlan_entry():
drivers/net/dsa/netc/netc_main.c:netc_add_standalone_vlan_entry() {
...
err = ntmp_vft_add_entry(&priv->ntmp, vft);
if (err)
return err;
}
If ntmp_bpt_update_entry() fails (for example, DMA allocation failure or
hardware timeout), netc_switch_bpt_default_config() will return success to
netc_setup(). The driver's bpt_list will have threshold values that do not
match the hardware state. Later, netc_port_set_tx_pause() called from
netc_mac_link_up() will read stale bpt_list data and attempt to update based
on incorrect assumptions about hardware configuration.
Should this follow the same error checking pattern as the other NTMP table
operations?
> +
> + netc_ipv_to_buffer_pool_mapping(priv);
> +
> + return 0;
> +}
[ ... ]
> @@ -1241,6 +1327,40 @@ static void netc_port_set_hd_flow_control(struct netc_port *np, bool en)
> en ? PM_CMD_CFG_HD_FCEN : 0);
> }
>
> +static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause)
> +{
> + struct netc_switch *priv = np->switch_priv;
> + int port = np->dp->index;
> + int i, j, num_bp;
> +
> + num_bp = priv->num_bp / priv->info->num_ports;
> + for (i = 0, j = port * num_bp; i < num_bp; i++, j++) {
> + struct bpt_cfge_data *cfge;
> +
> + cfge = &priv->bpt_list[j];
> + if (tx_pause) {
> + cfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON);
> + cfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF);
> + cfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG,
> + BPT_FC_CFG_EN_BPFC);
> + cfge->fc_ports = cpu_to_le32(BIT(port));
> + } else {
> + cfge->fc_on_thresh = cpu_to_le16(0);
> + cfge->fc_off_thresh = cpu_to_le16(0);
> + cfge->fccfg_sbpen = 0;
> + cfge->fc_ports = cpu_to_le32(0);
> + }
> +
> + ntmp_bpt_update_entry(&priv->ntmp, j, cfge);
> + }
> +}
[ ... ]
On 18/03/2026 15:54, Simon Horman wrote: > This is an AI-generated review of your patch. The human sending this > email has considered the AI review valid, or at least plausible. > Why are you removing the "PATCH" part in the email subject? This completely messes up with the filters and causes this email to pop up in places it should not. Best regards, Krzysztof
On Wed, Mar 18, 2026 at 03:56:39PM +0100, Krzysztof Kozlowski wrote: > On 18/03/2026 15:54, Simon Horman wrote: > > This is an AI-generated review of your patch. The human sending this > > email has considered the AI review valid, or at least plausible. > > > > Why are you removing the "PATCH" part in the email subject? > > This completely messes up with the filters and causes this email to pop > up in places it should not. Thanks for pointing this out. I sent this patch using some tooling. I'll look into why this happened.
On Wed, 18 Mar 2026 15:56:39 +0100 Krzysztof Kozlowski wrote: > On 18/03/2026 15:54, Simon Horman wrote: > > This is an AI-generated review of your patch. The human sending this > > email has considered the AI review valid, or at least plausible. > > Why are you removing the "PATCH" part in the email subject? > > This completely messes up with the filters and causes this email to pop > up in places it should not. Sorry about that :/ We pull patch info form patchwork and for some reason patchwork uses this notation for the "name" of the patch when showing the list of patches in series info. I'll hack up the scripts to fetch real thing from lore.
On Wed, Mar 18, 2026 at 03:24:08PM -0700, Jakub Kicinski wrote: > On Wed, 18 Mar 2026 15:56:39 +0100 Krzysztof Kozlowski wrote: > > On 18/03/2026 15:54, Simon Horman wrote: > > > This is an AI-generated review of your patch. The human sending this > > > email has considered the AI review valid, or at least plausible. > > > > Why are you removing the "PATCH" part in the email subject? > > > > This completely messes up with the filters and causes this email to pop > > up in places it should not. > > Sorry about that :/ We pull patch info form patchwork and for some > reason patchwork uses this notation for the "name" of the patch > when showing the list of patches in series info. > > I'll hack up the scripts to fetch real thing from lore. Thanks!
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