From: Jia Wang <wangjia@ultrarisc.com>
Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
.../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..b50ff98dd878
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description: |
+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+ This binding describes the UltraRISC specific extensions to the base DesignWare
+ PCIe binding.
+
+maintainers:
+ - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+ - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: ultrarisc,dp1000-pcie
+
+ reg:
+ - description: Data Bus Interface (DBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+
+ num-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of lanes to use.
+ Valid values: 4, 16.
+
+ max-link-speed:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 4
+ description:
+ Maximum PCIe link speed supported. 4 for Gen4.
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: inta
+ - const: intb
+ - const: intc
+ - const: intd
+
+ device_type:
+ const: pci
+
+ dma-coherent:
+ type: boolean
+
+ bus-range:
+ description:
+ PCI bus range associated with this controller.
+
+ interrupt-map-mask:
+ description:
+ PCI interrupt map mask for this controller.
+
+ interrupt-map:
+ description:
+ PCI interrupt map for this controller.
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - device_type
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pcie_x16: pcie@21000000 {
+ compatible = "ultrarisc,dp1000-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */
+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */
+ reg-names = "dbi", "config";
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ num-lanes = <16>;
+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */
+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */
+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */
+ max-link-speed = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <43>, <44>, <45>, <46>, <47>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+ <0x0 0x0 0x0 0x2 &plic 45>,
+ <0x0 0x0 0x0 0x3 &plic 46>,
+ <0x0 0x0 0x0 0x4 &plic 47>;
+ };
--
2.34.1On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote: > From: Jia Wang <wangjia@ultrarisc.com> > > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > --- > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > new file mode 100644 > index 000000000000..b50ff98dd878 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: UltraRISC DP1000 PCIe Host Controller > + > +description: | > + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. If so, you should probably refer snps,dw-pcie.yaml to avoid some duplication. Regards, Yao Zi
On 2026-03-17 04:56 +0000, Yao Zi wrote: > On Mon, Mar 16, 2026 at 03:06:59PM +0800, Jia Wang via B4 Relay wrote: > > From: Jia Wang <wangjia@ultrarisc.com> > > > > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > > --- > > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > > new file mode 100644 > > index 000000000000..b50ff98dd878 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > > @@ -0,0 +1,108 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: UltraRISC DP1000 PCIe Host Controller > > + > > +description: | > > + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. > > If so, you should probably refer snps,dw-pcie.yaml to avoid > some duplication. Thanks for the suggestion. I will reference snps,dw-pcie.yaml in v2. > > Regards, > Yao Zi > Regards, Jia
On 16/03/2026 08:06, Jia Wang via B4 Relay wrote: > From: Jia Wang <wangjia@ultrarisc.com> > > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > --- > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > new file mode 100644 > index 000000000000..b50ff98dd878 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: UltraRISC DP1000 PCIe Host Controller > + > +description: | > + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. > + This binding describes the UltraRISC specific extensions to the base DesignWare > + PCIe binding. > + > +maintainers: > + - Xincheng Zhang <zhangxincheng@ultrarisc.com> > + - Jia Wang <wangjia@ultrarisc.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + const: ultrarisc,dp1000-pcie > + > + reg: > + - description: Data Bus Interface (DBI) registers. > + - description: PCIe configuration space region. Never tested. Test your patches before sending to avoid common mistakes. Several issues here are just duplicating known issue. Read also sashiko review of your code. https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com Best regards, Krzysztof
On 2026-03-16 11:05 +0100, Krzysztof Kozlowski wrote: > On 16/03/2026 08:06, Jia Wang via B4 Relay wrote: > > From: Jia Wang <wangjia@ultrarisc.com> > > > > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > > --- > > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > > new file mode 100644 > > index 000000000000..b50ff98dd878 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > > @@ -0,0 +1,108 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: UltraRISC DP1000 PCIe Host Controller > > + > > +description: | > > + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. > > + This binding describes the UltraRISC specific extensions to the base DesignWare > > + PCIe binding. > > + > > +maintainers: > > + - Xincheng Zhang <zhangxincheng@ultrarisc.com> > > + - Jia Wang <wangjia@ultrarisc.com> > > + > > +allOf: > > + - $ref: /schemas/pci/pci-bus.yaml# > > + > > +properties: > > + compatible: > > + const: ultrarisc,dp1000-pcie > > + > > + reg: > > + - description: Data Bus Interface (DBI) registers. > > + - description: PCIe configuration space region. > > Never tested. Test your patches before sending to avoid common mistakes. > Several issues here are just duplicating known issue. > > Read also sashiko review of your code. > > https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com > Thanks for the review and the pointer. I have checked the Sashiko report and will fix all issues in the next version. > Best regards, > Krzysztof > Best regards, Jia
On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote: > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > --- > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > 1 file changed, 108 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation) ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts' Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1 make[2]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2 make: *** [Makefile:248: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 2026-03-16 03:21 -0500, Rob Herring (Arm) wrote: > > On Mon, 16 Mar 2026 15:06:59 +0800, Jia Wang wrote: > > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. > > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > > --- > > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 108 +++++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:26:7: [warning] wrong indentation: expected 4 but found 6 (indentation) > ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: [error] syntax error: mapping values are not allowed here (syntax) > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml: ignoring, error parsing file > make[2]: *** Deleting file 'Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts' > Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here > make[2]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.example.dts] Error 1 > make[2]: *** Waiting for unfinished jobs.... > ./Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml:38:19: mapping values are not allowed here > make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1606: dt_binding_check] Error 2 > make: *** [Makefile:248: __sub-make] Error 2 > > doc reference errors (make refcheckdocs): > > See https://patchwork.kernel.org/project/devicetree/patch/20260316-ultrarisc-pcie-v1-3-ef2946ede698@ultrarisc.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > > Thanks for the report. I’ve re-run `make dt_binding_check` locally with updated `yamllint` and `dtschema`, and I can reproduce the issues you pointed out. I will fix the indentation and correct the syntax error, re-validate the schema using the full `dt_binding_check`, and send a v2. Thanks for the guidance. Best regards, Jia
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