[v1] riscv: Add PCIe support for UltraRISC DP1000 SoC

[PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

Posted by Jia Wang via B4 Relay 3 weeks ago

From: Jia Wang <wangjia@ultrarisc.com>

The first SoC in the UltraRISC series is UR-DP1000, containing octa
UltraRISC C100 cores.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
 arch/riscv/Kconfig.socs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index d621b85dd63b..f49d3ccaacde 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -84,6 +84,16 @@ config ARCH_THEAD
 	help
 	  This enables support for the RISC-V based T-HEAD SoCs.
 
+config ARCH_ULTRARISC
+	bool "UltraRISC RISC-V SoCs"
+	depends on MMU && !XIP_KERNEL
+	help
+	 This enables support for UltraRISC SoC platform hardware,
+	 including boards based on the UR-DP1000.
+	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
+	 the RV64GCBHX ISA. It supports Hardware Virtualization
+	 and RISC-V RV64 ISA H(v1.0) Extension.
+
 config ARCH_VIRT
 	bool "QEMU Virt Machine"
 	select POWER_RESET

-- 
2.34.1

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

Posted by Conor Dooley 3 weeks ago

On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> The first SoC in the UltraRISC series is UR-DP1000, containing octa
> UltraRISC C100 cores.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
>  arch/riscv/Kconfig.socs | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index d621b85dd63b..f49d3ccaacde 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -84,6 +84,16 @@ config ARCH_THEAD
>  	help
>  	  This enables support for the RISC-V based T-HEAD SoCs.
>  
> +config ARCH_ULTRARISC
> +	bool "UltraRISC RISC-V SoCs"
> +	depends on MMU && !XIP_KERNEL

Why do you depend on "MMU && !XIP_KERNEL"?

> +	help
> +	 This enables support for UltraRISC SoC platform hardware,
> +	 including boards based on the UR-DP1000.
> +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> +	 and RISC-V RV64 ISA H(v1.0) Extension.
> +
>  config ARCH_VIRT
>  	bool "QEMU Virt Machine"
>  	select POWER_RESET
> 
> -- 
> 2.34.1
>

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

Posted by Jia Wang 2 weeks, 6 days ago

On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > UltraRISC C100 cores.
> > 
> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > ---
> >  arch/riscv/Kconfig.socs | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index d621b85dd63b..f49d3ccaacde 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -84,6 +84,16 @@ config ARCH_THEAD
> >  	help
> >  	  This enables support for the RISC-V based T-HEAD SoCs.
> >  
> > +config ARCH_ULTRARISC
> > +	bool "UltraRISC RISC-V SoCs"
> > +	depends on MMU && !XIP_KERNEL
> 
> Why do you depend on "MMU && !XIP_KERNEL"?
>
Hi Conor,

Thanks for the review.

The dependency on "MMU" was added conservatively, but the DP1000 hardware
does not strictly require MMU. I will remove this dependency in the
next version of the patch.

The "!XIP_KERNEL" dependency is retained because the platform does not
support executing the kernel directly from storage, so the kernel
must be loaded into RAM before execution.

Best regards,
Jia 
> > +	help
> > +	 This enables support for UltraRISC SoC platform hardware,
> > +	 including boards based on the UR-DP1000.
> > +	 UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > +	 the RV64GCBHX ISA. It supports Hardware Virtualization
> > +	 and RISC-V RV64 ISA H(v1.0) Extension.
> > +
> >  config ARCH_VIRT
> >  	bool "QEMU Virt Machine"
> >  	select POWER_RESET
> > 
> > -- 
> > 2.34.1
> >

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

Posted by Conor Dooley 2 weeks, 6 days ago

On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > UltraRISC C100 cores.
> > > 
> > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > ---
> > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > >  1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index d621b85dd63b..f49d3ccaacde 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > >  	help
> > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > >  
> > > +config ARCH_ULTRARISC
> > > +	bool "UltraRISC RISC-V SoCs"
> > > +	depends on MMU && !XIP_KERNEL
> > 
> > Why do you depend on "MMU && !XIP_KERNEL"?
> >
> Hi Conor,
> 
> Thanks for the review.
> 
> The dependency on "MMU" was added conservatively, but the DP1000 hardware
> does not strictly require MMU. I will remove this dependency in the
> next version of the patch.
> 
> The "!XIP_KERNEL" dependency is retained because the platform does not
> support executing the kernel directly from storage, so the kernel
> must be loaded into RAM before execution.

I would imagine the reason these are here is because you copied this
from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
is because they have errata that require alternatives to resolve, and
alternatives require those conditions. IMO you should remove these entirely,
especially since XIP_KERNEL is about to be removed for riscv soon
anyway.

Re: [PATCH 1/4] riscv: add UltraRISC SoC family Kconfig support

Posted by Jia Wang 2 weeks, 4 days ago

On 2026-03-17 13:02 +0000, Conor Dooley wrote:
> On Tue, Mar 17, 2026 at 02:46:24PM +0800, Jia Wang wrote:
> > On 2026-03-16 14:39 +0000, Conor Dooley wrote:
> > > On Mon, Mar 16, 2026 at 03:06:57PM +0800, Jia Wang wrote:
> > > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > > UltraRISC C100 cores.
> > > > 
> > > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > > ---
> > > >  arch/riscv/Kconfig.socs | 10 ++++++++++
> > > >  1 file changed, 10 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index d621b85dd63b..f49d3ccaacde 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -84,6 +84,16 @@ config ARCH_THEAD
> > > >  	help
> > > >  	  This enables support for the RISC-V based T-HEAD SoCs.
> > > >  
> > > > +config ARCH_ULTRARISC
> > > > +	bool "UltraRISC RISC-V SoCs"
> > > > +	depends on MMU && !XIP_KERNEL
> > > 
> > > Why do you depend on "MMU && !XIP_KERNEL"?
> > >
> > Hi Conor,
> > 
> > Thanks for the review.
> > 
> > The dependency on "MMU" was added conservatively, but the DP1000 hardware
> > does not strictly require MMU. I will remove this dependency in the
> > next version of the patch.
> > 
> > The "!XIP_KERNEL" dependency is retained because the platform does not
> > support executing the kernel directly from storage, so the kernel
> > must be loaded into RAM before execution.
> 
> I would imagine the reason these are here is because you copied this
> from one of the other entries. They have "depends on MMU && !XIP_KERNEL"
> is because they have errata that require alternatives to resolve, and
> alternatives require those conditions. IMO you should remove these entirely,
> especially since XIP_KERNEL is about to be removed for riscv soon
> anyway.
Thanks for the clarification.

I will remove the entire "depends on MMU && !XIP_KERNEL" line in the next
revision.

Thanks again for the guidance.

Best regards,
Jia