LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
Each group of pins is named in the reference manual after a primary
function using soc-specific naming, e.g. IIC1 (for i2c0).
Hardware block numbering starts from zero in device-tree but one in the
reference manual.
Rename the already defined pinmux nodes originally added for changing
i2c pins between i2c and gpio functions reflecting the reference manual
name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
label.
This makes it more clear to future developers that these nodes do in
fact configure a group of pins, and helps with cross-referencing
documentation.
No functional change intended.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 41c9b4253f4a5..28500e8873909 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_scl>;
- pinctrl-1 = <&i2c0_scl_gpio>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -766,8 +766,8 @@ i2c1: i2c@2010000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_scl>;
- pinctrl-1 = <&i2c1_scl_gpio>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -782,8 +782,8 @@ i2c2: i2c@2020000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_scl>;
- pinctrl-1 = <&i2c2_scl_gpio>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -798,8 +798,8 @@ i2c3: i2c@2030000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c3_scl>;
- pinctrl-1 = <&i2c3_scl_gpio>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -814,8 +814,8 @@ i2c4: i2c@2040000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c4_scl>;
- pinctrl-1 = <&i2c4_scl_gpio>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -830,8 +830,8 @@ i2c5: i2c@2050000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c5_scl>;
- pinctrl-1 = <&i2c5_scl_gpio>;
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -846,8 +846,8 @@ i2c6: i2c@2060000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -862,8 +862,8 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1713,11 +1713,11 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
- i2c1_scl: i2c1-scl-pins {
+ i2c1_pins: iic2-i2c-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
- i2c1_scl_gpio: i2c1-scl-gpio-pins {
+ gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
@@ -1725,35 +1725,35 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
- i2c2_scl: i2c2-scl-pins {
+ i2c2_pins: iic3-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
- i2c2_scl_gpio: i2c2-scl-gpio-pins {
+ gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
- i2c3_scl: i2c3-scl-pins {
+ i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
- i2c3_scl_gpio: i2c3-scl-gpio-pins {
+ gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
- i2c4_scl: i2c4-scl-pins {
+ i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
- i2c4_scl_gpio: i2c4-scl-gpio-pins {
+ gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
- i2c5_scl: i2c5-scl-pins {
+ i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
- i2c5_scl_gpio: i2c5-scl-gpio-pins {
+ gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
@@ -1777,19 +1777,19 @@ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
- i2c6_scl: i2c6-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ pinctrl-single,bits = <0x4 0x1 0x7>;
};
- i2c6_scl_gpio: i2c6-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ pinctrl-single,bits = <0x4 0x2 0x7>;
};
- i2c0_scl: i2c0-scl-pins {
+ i2c0_pins: iic1-i2c-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
- i2c0_scl_gpio: i2c0-scl-gpio-pins {
+ gpio0_3_2_pins: iic1-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0On Sat, Mar 14, 2026 at 01:05:14PM +0100, Josua Mayer wrote:
> LX2160A pinmux is done in groups by various length bitfields within
> configuration registers.
>
> Each group of pins is named in the reference manual after a primary
> function using soc-specific naming, e.g. IIC1 (for i2c0).
>
> Hardware block numbering starts from zero in device-tree but one in the
> reference manual.
>
> Rename the already defined pinmux nodes originally added for changing
> i2c pins between i2c and gpio functions reflecting the reference manual
> name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
> label.
>
> This makes it more clear to future developers that these nodes do in
> fact configure a group of pins, and helps with cross-referencing
> documentation.
>
> No functional change intended.
>
> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
> 1 file changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 41c9b4253f4a5..28500e8873909 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> QORIQ_CLK_PLL_DIV(16)>;
> pinctrl-names = "default", "gpio";
> - pinctrl-0 = <&i2c0_scl>;
> - pinctrl-1 = <&i2c0_scl_gpio>;
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&gpio0_3_2_pins>;
why need change label name here. It should scl, why need change to pins?
Frank
Hi Frank,
On 3/17/26 02:36, Frank Li wrote:
> On Sat, Mar 14, 2026 at 01:05:14PM +0100, Josua Mayer wrote:
>> LX2160A pinmux is done in groups by various length bitfields within
>> configuration registers.
>>
>> Each group of pins is named in the reference manual after a primary
>> function using soc-specific naming, e.g. IIC1 (for i2c0).
>>
>> Hardware block numbering starts from zero in device-tree but one in the
>> reference manual.
>>
>> Rename the already defined pinmux nodes originally added for changing
>> i2c pins between i2c and gpio functions reflecting the reference manual
>> name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
>> label.
>>
>> This makes it more clear to future developers that these nodes do in
>> fact configure a group of pins, and helps with cross-referencing
>> documentation.
>>
>> No functional change intended.
>>
>> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
>> 1 file changed, 32 insertions(+), 32 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index 41c9b4253f4a5..28500e8873909 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
>> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
>> QORIQ_CLK_PLL_DIV(16)>;
>> pinctrl-names = "default", "gpio";
>> - pinctrl-0 = <&i2c0_scl>;
>> - pinctrl-1 = <&i2c0_scl_gpio>;
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-1 = <&gpio0_3_2_pins>;
> why need change label name here. It should scl, why need change to pins?
Readability.
It should definitely not be called "scl" precisely because the node
previously labeled i2c0_scl actually configures both sda and scl together.
And plain "&i2c0" is already taken, so I added _pins.
For the gpios I also changed the label because we are in SoC dtsi,
and gpios are not specific to sda or scl function.
Further including the gpio numbers in the label helps spotting mistakes.
This patch-set is a story explaining chapter by chapter why initially
I just reverted the original commit.
sincerely
Josua Mayer
On Tue, Mar 17, 2026 at 05:20:20PM +0000, Josua Mayer wrote:
> Hi Frank,
>
> On 3/17/26 02:36, Frank Li wrote:
> > On Sat, Mar 14, 2026 at 01:05:14PM +0100, Josua Mayer wrote:
> >> LX2160A pinmux is done in groups by various length bitfields within
> >> configuration registers.
> >>
> >> Each group of pins is named in the reference manual after a primary
> >> function using soc-specific naming, e.g. IIC1 (for i2c0).
> >>
> >> Hardware block numbering starts from zero in device-tree but one in the
> >> reference manual.
> >>
> >> Rename the already defined pinmux nodes originally added for changing
> >> i2c pins between i2c and gpio functions reflecting the reference manual
> >> name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
> >> label.
> >>
> >> This makes it more clear to future developers that these nodes do in
Needn't 'this' just
Make it more ...
> >> fact configure a group of pins, and helps with cross-referencing
> >> documentation.
> >>
> >> No functional change intended.
> >>
> >> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
> >> Signed-off-by: Josua Mayer <josua@solid-run.com>
> >> ---
> >> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
> >> 1 file changed, 32 insertions(+), 32 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >> index 41c9b4253f4a5..28500e8873909 100644
> >> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >> @@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
> >> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> >> QORIQ_CLK_PLL_DIV(16)>;
> >> pinctrl-names = "default", "gpio";
> >> - pinctrl-0 = <&i2c0_scl>;
> >> - pinctrl-1 = <&i2c0_scl_gpio>;
> >> + pinctrl-0 = <&i2c0_pins>;
> >> + pinctrl-1 = <&gpio0_3_2_pins>;
> > why need change label name here. It should scl, why need change to pins?
>
> Readability.
>
> It should definitely not be called "scl" precisely because the node
> previously labeled i2c0_scl actually configures both sda and scl together.
This need mention in commit message about why rename.
Frank
>
> And plain "&i2c0" is already taken, so I added _pins.
>
> For the gpios I also changed the label because we are in SoC dtsi,
> and gpios are not specific to sda or scl function.
>
> Further including the gpio numbers in the label helps spotting mistakes.
>
> This patch-set is a story explaining chapter by chapter why initially
> I just reverted the original commit.
>
> sincerely
> Josua Mayer
Am 18.03.26 um 14:48 schrieb Frank Li:
> On Tue, Mar 17, 2026 at 05:20:20PM +0000, Josua Mayer wrote:
>> Hi Frank,
>>
>> On 3/17/26 02:36, Frank Li wrote:
>>> On Sat, Mar 14, 2026 at 01:05:14PM +0100, Josua Mayer wrote:
>>>> LX2160A pinmux is done in groups by various length bitfields within
>>>> configuration registers.
>>>>
>>>> Each group of pins is named in the reference manual after a primary
>>>> function using soc-specific naming, e.g. IIC1 (for i2c0).
>>>>
>>>> Hardware block numbering starts from zero in device-tree but one in the
>>>> reference manual.
>>>>
>>>> Rename the already defined pinmux nodes originally added for changing
>>>> i2c pins between i2c and gpio functions reflecting the reference manual
>>>> name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
>>>> label.
>>>>
>>>> This makes it more clear to future developers that these nodes do in
> Needn't 'this' just
>
> Make it more ...
Okay, I'll rephrase it. "Make it more clear" was an intended result from renaming,
not the action itself.
>
>>>> fact configure a group of pins, and helps with cross-referencing
>>>> documentation.
>>>>
>>>> No functional change intended.
>>>>
>>>> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
>>>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>>>> ---
>>>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
>>>> 1 file changed, 32 insertions(+), 32 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> index 41c9b4253f4a5..28500e8873909 100644
>>>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> @@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
>>>> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
>>>> QORIQ_CLK_PLL_DIV(16)>;
>>>> pinctrl-names = "default", "gpio";
>>>> - pinctrl-0 = <&i2c0_scl>;
>>>> - pinctrl-1 = <&i2c0_scl_gpio>;
>>>> + pinctrl-0 = <&i2c0_pins>;
>>>> + pinctrl-1 = <&gpio0_3_2_pins>;
>>> why need change label name here. It should scl, why need change to pins?
>> Readability.
>>
>> It should definitely not be called "scl" precisely because the node
>> previously labeled i2c0_scl actually configures both sda and scl together.
> This need mention in commit message about why rename.
Okay.
>
> Frank
>> And plain "&i2c0" is already taken, so I added _pins.
>>
>> For the gpios I also changed the label because we are in SoC dtsi,
>> and gpios are not specific to sda or scl function.
>>
>> Further including the gpio numbers in the label helps spotting mistakes.
>>
>> This patch-set is a story explaining chapter by chapter why initially
>> I just reverted the original commit.
>>
>> sincerely
>> Josua Mayer
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