Hi Jacopo and Barnabás
On 13/03/2026 11:14, Jacopo Mondi wrote:
> From: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
>
> Bit 20 should be written in this register to stop frame processing.
> So fix that, as well as the poll condition.
>
> Cc: stable@vger.kernel.org
> Fixes: f0b3984d821b ("media: platform: Add Renesas Input Video Control block driver")
> Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
> ---
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
> drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c | 5 +++--
> drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h | 1 +
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
> index d894a880c33f..9b75e4b10e99 100644
> --- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
> +++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
> @@ -297,9 +297,10 @@ static void rzv2h_ivc_stop_streaming(struct vb2_queue *q)
> struct rzv2h_ivc *ivc = vb2_get_drv_priv(q);
> u32 val = 0;
>
> - rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, 0x1);
> + rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, RZV2H_IVC_REG_FM_STOP_FSTOP);
> readl_poll_timeout(ivc->base + RZV2H_IVC_REG_FM_STOP,
> - val, !val, 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
> + val, !(val & RZV2H_IVC_REG_FM_STOP_FSTOP),
> + 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
>
> rzv2h_ivc_return_buffers(ivc, VB2_BUF_STATE_ERROR);
> video_device_pipeline_stop(&ivc->vdev.dev);
> diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
> index 54c70de31c1e..049f223200e3 100644
> --- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
> +++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
> @@ -46,6 +46,7 @@
> #define RZV2H_IVC_REG_FM_MCON 0x0104
> #define RZV2H_IVC_REG_FM_FRCON 0x0108
> #define RZV2H_IVC_REG_FM_STOP 0x010c
> +#define RZV2H_IVC_REG_FM_STOP_FSTOP BIT(20)
> #define RZV2H_IVC_REG_FM_INT_EN 0x0120
> #define RZV2H_IVC_VVAL_IFPE BIT(0)
> #define RZV2H_IVC_REG_FM_INT_STA 0x0124
>