DesignWare endpoint controllers already expose the controller MMIO
region and the per-channel linked-list descriptor windows as auxiliary
resources. Populate the new DMA channel metadata for each
PCI_EPC_AUX_DMA_CHAN_DESC entry using the cached channel IDs and channel
direction.
This lets generic consumers match delegated DMA channels to the
descriptor windows they need to program.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index eec20800a745..1e584f6a6565 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -947,6 +947,10 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
.size = edma->ll_region_wr[i].sz,
.bar = NO_BAR,
.bar_offset = 0,
+ .u.dma_chan = {
+ .chan_id = edma->chan_ids_wr[i],
+ .dir = PCI_EPC_AUX_DMA_DIR_WRITE,
+ },
};
}
@@ -961,6 +965,10 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
.size = edma->ll_region_rd[i].sz,
.bar = NO_BAR,
.bar_offset = 0,
+ .u.dma_chan = {
+ .chan_id = edma->chan_ids_rd[i],
+ .dir = PCI_EPC_AUX_DMA_DIR_READ,
+ },
};
}
--
2.51.0