From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add clocks and reset entries for the PCIe controller.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a09g057-cpg.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index c3174f40fdb4..2fa5a620bbd9 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -508,6 +508,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(6))),
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
+ BUS_MSTOP(1, BIT(13) | BIT(15))),
+ DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
+ BUS_MSTOP(1, BIT(13) | BIT(15))),
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
BUS_MSTOP(9, BIT(4))),
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -642,6 +646,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
+ DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
--
2.53.0On 3/12/26 13:15, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add clocks and reset entries for the PCIe controller. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi Prabhakar,
On Thu, 12 Mar 2026 at 12:15, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clocks and reset entries for the PCIe controller.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -508,6 +508,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(6))),
> DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
> + BUS_MSTOP(1, BIT(13) | BIT(15))),
> + DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
> + BUS_MSTOP(1, BIT(13) | BIT(15))),
So the PCIE0 and PCIE1 modules are always stopped/started together, oh well...
> DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> BUS_MSTOP(9, BIT(4))),
> DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v7.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Wed, Mar 18, 2026 at 2:35 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, 12 Mar 2026 at 12:15, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add clocks and reset entries for the PCIe controller.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > @@ -508,6 +508,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> > BUS_MSTOP(8, BIT(6))),
> > DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> > BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
> > + BUS_MSTOP(1, BIT(13) | BIT(15))),
> > + DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
> > + BUS_MSTOP(1, BIT(13) | BIT(15))),
>
> So the PCIE0 and PCIE1 modules are always stopped/started together, oh well...
>
Yes the clocks and reset are shared.
Cheers,
Prabhakar
> > DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> > BUS_MSTOP(9, BIT(4))),
> > DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-clk for v7.1.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
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