Add deepest idle state along with pdc config reg to make GPIO IRQs work
as wakeup capable interrupts in deepest idle state.
Add QMP handle to allow PDC device to place a SoC level low power mode
restriction.
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index ebecf43e0d462c431540257e299e3ace054901fd..8f560fd140661ad720fec979eabe3ca8ffb34273 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -290,6 +290,14 @@ cluster_cl5: cluster-sleep-1 {
exit-latency-us = <4000>;
min-residency-us = <7000>;
};
+
+ domain_ss3: domain-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x0200c354>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <9000>;
+ };
};
};
@@ -447,7 +455,7 @@ cluster_pd2: power-domain-cpu-cluster2 {
system_pd: power-domain-system {
#power-domain-cells = <0>;
- /* TODO: system-wide idle states */
+ domain-idle-states = <&domain_ss3>;
};
};
@@ -6013,8 +6021,10 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
-
+ reg = <0 0x0b220000 0 0x30000>,
+ <0 0x174000f0 0 0x64>,
+ <0 0x0b2045e8 0 0x4>;
+ qcom,qmp = <&aoss_qmp>;
qcom,pdc-ranges = <0 480 42>, <42 251 5>,
<47 522 52>, <99 609 32>,
<131 717 12>, <143 816 19>;
--
2.34.1On Thu, Mar 12, 2026 at 09:26:38PM +0530, Maulik Shah wrote:
> Add deepest idle state along with pdc config reg to make GPIO IRQs work
> as wakeup capable interrupts in deepest idle state.
>
> Add QMP handle to allow PDC device to place a SoC level low power mode
> restriction.
>
> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/hamoa.dtsi | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index ebecf43e0d462c431540257e299e3ace054901fd..8f560fd140661ad720fec979eabe3ca8ffb34273 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -290,6 +290,14 @@ cluster_cl5: cluster-sleep-1 {
> exit-latency-us = <4000>;
> min-residency-us = <7000>;
> };
> +
> + domain_ss3: domain-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x0200c354>;
> + entry-latency-us = <2800>;
> + exit-latency-us = <4400>;
> + min-residency-us = <9000>;
> + };
> };
> };
>
> @@ -447,7 +455,7 @@ cluster_pd2: power-domain-cpu-cluster2 {
>
> system_pd: power-domain-system {
> #power-domain-cells = <0>;
> - /* TODO: system-wide idle states */
> + domain-idle-states = <&domain_ss3>;
> };
> };
>
> @@ -6013,8 +6021,10 @@ dispcc: clock-controller@af00000 {
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,x1e80100-pdc", "qcom,pdc";
> - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> -
> + reg = <0 0x0b220000 0 0x30000>,
> + <0 0x174000f0 0 0x64>,
> + <0 0x0b2045e8 0 0x4>;
One register is not device's address space.
Best regards,
Krzysztof
On 3/13/2026 7:27 PM, Krzysztof Kozlowski wrote:
> On Thu, Mar 12, 2026 at 09:26:38PM +0530, Maulik Shah wrote:
>> Add deepest idle state along with pdc config reg to make GPIO IRQs work
>> as wakeup capable interrupts in deepest idle state.
>>
...
...
>>
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,x1e80100-pdc", "qcom,pdc";
>> - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
>> -
>> + reg = <0 0x0b220000 0 0x30000>,
>> + <0 0x174000f0 0 0x64>,
>> + <0 0x0b2045e8 0 0x4>;
>
> One register is not device's address space.
>
I can move this one register as #define in driver in v2, SCM API is the only use
for this reg.
Thanks,
Maulik
On Thu, Mar 12, 2026 at 09:26:38PM +0530, Maulik Shah wrote:
> Add deepest idle state along with pdc config reg to make GPIO IRQs work
> as wakeup capable interrupts in deepest idle state.
>
> Add QMP handle to allow PDC device to place a SoC level low power mode
> restriction.
>
> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/hamoa.dtsi | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index ebecf43e0d462c431540257e299e3ace054901fd..8f560fd140661ad720fec979eabe3ca8ffb34273 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -290,6 +290,14 @@ cluster_cl5: cluster-sleep-1 {
> exit-latency-us = <4000>;
> min-residency-us = <7000>;
> };
> +
> + domain_ss3: domain-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x0200c354>;
> + entry-latency-us = <2800>;
> + exit-latency-us = <4400>;
> + min-residency-us = <9000>;
> + };
> };
> };
>
> @@ -447,7 +455,7 @@ cluster_pd2: power-domain-cpu-cluster2 {
>
> system_pd: power-domain-system {
> #power-domain-cells = <0>;
> - /* TODO: system-wide idle states */
> + domain-idle-states = <&domain_ss3>;
> };
> };
>
> @@ -6013,8 +6021,10 @@ dispcc: clock-controller@af00000 {
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,x1e80100-pdc", "qcom,pdc";
> - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
> -
> + reg = <0 0x0b220000 0 0x30000>,
As you are touching these lines, 0x0 instead of just 0, please.
> + <0 0x174000f0 0 0x64>,
> + <0 0x0b2045e8 0 0x4>;
> + qcom,qmp = <&aoss_qmp>;
> qcom,pdc-ranges = <0 480 42>, <42 251 5>,
> <47 522 52>, <99 609 32>,
> <131 717 12>, <143 816 19>;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 3/13/2026 8:00 AM, Dmitry Baryshkov wrote: > On Thu, Mar 12, 2026 at 09:26:38PM +0530, Maulik Shah wrote: >> - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; >> - >> + reg = <0 0x0b220000 0 0x30000>, > > As you are touching these lines, 0x0 instead of just 0, please. Sure, Will update in v2. Thanks, Maulik
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