Instead of grouping several different reset lines into one composite
reset, decouple them to individual ones which make it more aligned
with underlying hardware.
The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
1 file changed, 32 insertions(+), 10 deletions(-)
diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
index 79ac1c22b7b5..c12f8bd32047 100644
--- a/include/dt-bindings/reset/spacemit,k3-resets.h
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -97,11 +97,7 @@
#define RESET_APMU_SDH0 13
#define RESET_APMU_SDH1 14
#define RESET_APMU_SDH2 15
-#define RESET_APMU_USB2 16
-#define RESET_APMU_USB3_PORTA 17
-#define RESET_APMU_USB3_PORTB 18
-#define RESET_APMU_USB3_PORTC 19
-#define RESET_APMU_USB3_PORTD 20
+/* Deprecated USB 16 - 20 */
#define RESET_APMU_QSPI 21
#define RESET_APMU_QSPI_BUS 22
#define RESET_APMU_DMA 23
@@ -143,16 +139,42 @@
#define RESET_APMU_UFS_ACLK 59
#define RESET_APMU_EDP0 60
#define RESET_APMU_EDP1 61
-#define RESET_APMU_PCIE_PORTA 62
-#define RESET_APMU_PCIE_PORTB 63
-#define RESET_APMU_PCIE_PORTC 64
-#define RESET_APMU_PCIE_PORTD 65
-#define RESET_APMU_PCIE_PORTE 66
+/* Deprecated PCIe 62 - 66 */
#define RESET_APMU_EMAC0 67
#define RESET_APMU_EMAC1 68
#define RESET_APMU_EMAC2 69
#define RESET_APMU_ESPI_MCLK 70
#define RESET_APMU_ESPI_SCLK 71
+#define RESET_APMU_USB2_AHB 72
+#define RESET_APMU_USB2_VCC 73
+#define RESET_APMU_USB2_PHY 74
+#define RESET_APMU_USB3_A_AHB 75
+#define RESET_APMU_USB3_A_VCC 76
+#define RESET_APMU_USB3_A_PHY 77
+#define RESET_APMU_USB3_B_AHB 78
+#define RESET_APMU_USB3_B_VCC 79
+#define RESET_APMU_USB3_B_PHY 80
+#define RESET_APMU_USB3_C_AHB 81
+#define RESET_APMU_USB3_C_VCC 82
+#define RESET_APMU_USB3_C_PHY 83
+#define RESET_APMU_USB3_D_AHB 84
+#define RESET_APMU_USB3_D_VCC 85
+#define RESET_APMU_USB3_D_PHY 86
+#define RESET_APMU_PCIE_A_DBI 87
+#define RESET_APMU_PCIE_A_SLAVE 88
+#define RESET_APMU_PCIE_A_MASTER 89
+#define RESET_APMU_PCIE_B_DBI 90
+#define RESET_APMU_PCIE_B_SLAVE 91
+#define RESET_APMU_PCIE_B_MASTER 92
+#define RESET_APMU_PCIE_C_DBI 93
+#define RESET_APMU_PCIE_C_SLAVE 94
+#define RESET_APMU_PCIE_C_MASTER 95
+#define RESET_APMU_PCIE_D_DBI 96
+#define RESET_APMU_PCIE_D_SLAVE 97
+#define RESET_APMU_PCIE_D_MASTER 98
+#define RESET_APMU_PCIE_E_DBI 99
+#define RESET_APMU_PCIE_E_SLAVE 100
+#define RESET_APMU_PCIE_E_MASTER 101
/* DCIU resets*/
#define RESET_DCIU_HDMA 0
--
2.53.0On Thu, Mar 12, 2026 at 10:34:19AM +0000, Yixun Lan wrote: > Instead of grouping several different reset lines into one composite > reset, decouple them to individual ones which make it more aligned > with underlying hardware. > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. Either this is ABI break, which would need explanation, or it is not, which also needs explanation and then fixing current bindings before they are released. Best regards, Krzysztof
Hi Krzysztof, On 14:42 Fri 13 Mar , Krzysztof Kozlowski wrote: > On Thu, Mar 12, 2026 at 10:34:19AM +0000, Yixun Lan wrote: > > Instead of grouping several different reset lines into one composite > > reset, decouple them to individual ones which make it more aligned > > with underlying hardware. > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > Either this is ABI break, which would need explanation, or it is not, > which also needs explanation and then fixing current bindings before > they are released. > Literally, Changing IDs would result an ABI breakage, but since we have no consumers - no driver/DT use those IDs so far, so we could safely renumber it and push as a fix for it. This issue was already raised by Philipp in this thread [1], and I agreeed, will put some explanations. Link: https://lore.kernel.org/r/20260312112858-GKH302167@kernel.org [1] -- Yixun Lan (dlan)
On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote: > Instead of grouping several different reset lines into one composite > reset, decouple them to individual ones which make it more aligned > with underlying hardware. > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > Signed-off-by: Yixun Lan <dlan@kernel.org> > --- > include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------ > 1 file changed, 32 insertions(+), 10 deletions(-) > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h > index 79ac1c22b7b5..c12f8bd32047 100644 > --- a/include/dt-bindings/reset/spacemit,k3-resets.h > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h > @@ -97,11 +97,7 @@ > #define RESET_APMU_SDH0 13 > #define RESET_APMU_SDH1 14 > #define RESET_APMU_SDH2 15 > -#define RESET_APMU_USB2 16 > -#define RESET_APMU_USB3_PORTA 17 > -#define RESET_APMU_USB3_PORTB 18 > -#define RESET_APMU_USB3_PORTC 19 > -#define RESET_APMU_USB3_PORTD 20 This is backwards incompatible. Are there any device trees using the APMU resets yet? If not, I wonder if we should just renumber all APMU resets into a contiguous range and try to get it into v7.0 as a fix. Also, this breaks bisectability. reset-spacemit-k3.c will fail to compile between patches 1 and 2. regards Philipp
Hi Philipp, On 12:09 Thu 12 Mar , Philipp Zabel wrote: > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote: > > Instead of grouping several different reset lines into one composite > > reset, decouple them to individual ones which make it more aligned > > with underlying hardware. > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > > > Signed-off-by: Yixun Lan <dlan@kernel.org> > > --- > > include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------ > > 1 file changed, 32 insertions(+), 10 deletions(-) > > > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h > > index 79ac1c22b7b5..c12f8bd32047 100644 > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h > > @@ -97,11 +97,7 @@ > > #define RESET_APMU_SDH0 13 > > #define RESET_APMU_SDH1 14 > > #define RESET_APMU_SDH2 15 > > -#define RESET_APMU_USB2 16 > > -#define RESET_APMU_USB3_PORTA 17 > > -#define RESET_APMU_USB3_PORTB 18 > > -#define RESET_APMU_USB3_PORTC 19 > > -#define RESET_APMU_USB3_PORTD 20 > > This is backwards incompatible. > Are there any device trees using the APMU resets yet? > If not, I wonder if we should just renumber all APMU resets into a > contiguous range and try to get it into v7.0 as a fix. > No, there is currently no consumers, so I could rework them into a contiguous version, thanks for the suggestion > Also, this breaks bisectability. > reset-spacemit-k3.c will fail to compile between patches 1 and 2. > I've tried a first version to squash the two patches, but got a checkpatch.pl complait for binding should follow into a separate patch. I can combine these two patches into one, is this Ok for you? -- Yixun Lan (dlan)
On Do, 2026-03-12 at 19:28 +0800, Yixun Lan wrote: > Hi Philipp, > > On 12:09 Thu 12 Mar , Philipp Zabel wrote: > > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote: > > > Instead of grouping several different reset lines into one composite > > > reset, decouple them to individual ones which make it more aligned > > > with underlying hardware. > > > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > > > > > Signed-off-by: Yixun Lan <dlan@kernel.org> > > > --- > > > include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------ > > > 1 file changed, 32 insertions(+), 10 deletions(-) > > > > > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h > > > index 79ac1c22b7b5..c12f8bd32047 100644 > > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h > > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h > > > @@ -97,11 +97,7 @@ > > > #define RESET_APMU_SDH0 13 > > > #define RESET_APMU_SDH1 14 > > > #define RESET_APMU_SDH2 15 > > > -#define RESET_APMU_USB2 16 > > > -#define RESET_APMU_USB3_PORTA 17 > > > -#define RESET_APMU_USB3_PORTB 18 > > > -#define RESET_APMU_USB3_PORTC 19 > > > -#define RESET_APMU_USB3_PORTD 20 > > > > This is backwards incompatible. > > Are there any device trees using the APMU resets yet? > > If not, I wonder if we should just renumber all APMU resets into a > > contiguous range and try to get it into v7.0 as a fix. > > > No, there is currently no consumers, Good, that will make things easier. > so I could rework them into a contiguous version, thanks for the suggestion > > > Also, this breaks bisectability. > > reset-spacemit-k3.c will fail to compile between patches 1 and 2. > > > I've tried a first version to squash the two patches, but got a checkpatch.pl complait > for binding should follow into a separate patch. > > I can combine these two patches into one, is this Ok for you? I'm in favor of fixing both the APMU defines and the only existing user, the reset driver, in a single patch. Explain it well, add Fixes: 216e0a5e98e5 and 938ce3b16582 tags, and then I can apply it on the reset/fixes branch in time for v7.0. regards Philipp
On Thu, Mar 12, 2026 at 07:28:58PM +0800, Yixun Lan wrote: > Hi Philipp, > > On 12:09 Thu 12 Mar , Philipp Zabel wrote: > > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote: > > > Instead of grouping several different reset lines into one composite > > > reset, decouple them to individual ones which make it more aligned > > > with underlying hardware. > > > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > > > > > Signed-off-by: Yixun Lan <dlan@kernel.org> > > > --- > > > include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------ > > > 1 file changed, 32 insertions(+), 10 deletions(-) > > > > > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h > > > index 79ac1c22b7b5..c12f8bd32047 100644 > > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h > > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h > > > @@ -97,11 +97,7 @@ > > > #define RESET_APMU_SDH0 13 > > > #define RESET_APMU_SDH1 14 > > > #define RESET_APMU_SDH2 15 > > > -#define RESET_APMU_USB2 16 > > > -#define RESET_APMU_USB3_PORTA 17 > > > -#define RESET_APMU_USB3_PORTB 18 > > > -#define RESET_APMU_USB3_PORTC 19 > > > -#define RESET_APMU_USB3_PORTD 20 > > > > This is backwards incompatible. > > Are there any device trees using the APMU resets yet? > > If not, I wonder if we should just renumber all APMU resets into a > > contiguous range and try to get it into v7.0 as a fix. > > > No, there is currently no consumers, so I could rework them into a contiguous > version, thanks for the suggestion Only as long as it goes into 7.0, IMO, as a fix. > > Also, this breaks bisectability. > > reset-spacemit-k3.c will fail to compile between patches 1 and 2. > > > I've tried a first version to squash the two patches, but got a checkpatch.pl complait > for binding should follow into a separate patch. > > I can combine these two patches into one, is this Ok for you? Be very very very clear about why they're going together, otherwise you'll get yelled at!
Hi Conor, On 17:30 Thu 12 Mar , Conor Dooley wrote: > On Thu, Mar 12, 2026 at 07:28:58PM +0800, Yixun Lan wrote: > > Hi Philipp, > > > > On 12:09 Thu 12 Mar , Philipp Zabel wrote: > > > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote: > > > > Instead of grouping several different reset lines into one composite > > > > reset, decouple them to individual ones which make it more aligned > > > > with underlying hardware. > > > > > > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, > > > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. > > > > > > > > Signed-off-by: Yixun Lan <dlan@kernel.org> > > > > --- > > > > include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------ > > > > 1 file changed, 32 insertions(+), 10 deletions(-) > > > > > > > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h > > > > index 79ac1c22b7b5..c12f8bd32047 100644 > > > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h > > > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h > > > > @@ -97,11 +97,7 @@ > > > > #define RESET_APMU_SDH0 13 > > > > #define RESET_APMU_SDH1 14 > > > > #define RESET_APMU_SDH2 15 > > > > -#define RESET_APMU_USB2 16 > > > > -#define RESET_APMU_USB3_PORTA 17 > > > > -#define RESET_APMU_USB3_PORTB 18 > > > > -#define RESET_APMU_USB3_PORTC 19 > > > > -#define RESET_APMU_USB3_PORTD 20 > > > > > > This is backwards incompatible. > > > Are there any device trees using the APMU resets yet? > > > If not, I wonder if we should just renumber all APMU resets into a > > > contiguous range and try to get it into v7.0 as a fix. > > > > > No, there is currently no consumers, so I could rework them into a contiguous > > version, thanks for the suggestion > > Only as long as it goes into 7.0, IMO, as a fix. > Yes, that's the plan In this case, I would change my mind to add a Fixes tag explicitly(shouldn't hurt!) > > > Also, this breaks bisectability. > > > reset-spacemit-k3.c will fail to compile between patches 1 and 2. > > > > > I've tried a first version to squash the two patches, but got a checkpatch.pl complait > > for binding should follow into a separate patch. > > > > I can combine these two patches into one, is this Ok for you? > > Be very very very clear about why they're going together, otherwise you'll > get yelled at! Ok, will add comment for this, thanks for the tip. -- Yixun Lan (dlan)
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