From: John Crispin <john@phrozen.org>
The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.
Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
generic schema.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
index 3827cb9fdff3..de338c05190f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,ipq5018-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq6018-cmn-pll
+ - qcom,ipq8074-cmn-pll
- qcom,ipq9574-cmn-pll
reg:
diff --git a/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
new file mode 100644
index 000000000000..354258a481c2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ8074_CMN_PLL_CLK 0
+
+/* The output clocks from CMN PLL of IPQ8074. */
+#define IPQ8074_BIAS_PLL_CC_CLK 1
+#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2
+#endif
--
2.53.0