From: Hangtian Zhu <hangtian@oss.qualcomm.com>

Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
platform.

Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
---
This patch depends on:
[PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

Changes in v3:
- Commit message changes, move Depends-on from commit message to
cover-letter.
- Introduce the PCIe architecture of RB3 Gen2 iindustrial mezzanine in
the cover letter.
- Link to v2: https://lore.kernel.org/all/20260311031145.2285056-1-hangtian.zhu@oss.qualcomm.com/

Changes in v2:
- Commit message changes, change rb3gen2 to RB3 Gen2; wcn6750 to
WCN6750; wpss to WPSS etc.
- Link to v1: https://lore.kernel.org/all/20260311023219.2284643-1-hangtian.zhu@oss.qualcomm.com/
---
 .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 2a2b7c2f9210..6594c7e1ea93 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -32,6 +32,10 @@ vreg_1p8: regulator-vreg-1p8 {
 	};
 };
 
+&remoteproc_wpss {
+       status = "disabled";
+};
+
 &spi11 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -280,3 +284,7 @@ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
 	};
 
 };
+
+&wifi {
+       status = "disabled";
+};
-- 
2.25.1

On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> 
> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> platform.
> 
> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> ---
> This patch depends on:
> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

If it is a fix for the patch which is still in flight, then stop posting
it as a separate patch. PLease work with the original series author to
get it squashed into the posted patch.

> 

-- 
With best wishes
Dmitry

On 3/12/2026 11:07, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>
>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
>> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
>> platform.
>>
>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
>> ---
>> This patch depends on:
>> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> 
> If it is a fix for the patch which is still in flight, then stop posting
> it as a separate patch. PLease work with the original series author to
> get it squashed into the posted patch.
The base changes are merged internally in QLI 2.0 already, it can't take additional changes. The base changes are PCIe specific, and this change is WLAN related.
> 
>>
>

On Thu, Mar 12, 2026 at 04:20:10PM +0800, Hangtian Zhu wrote:
> 
> 
> On 3/12/2026 11:07, Dmitry Baryshkov wrote:
> > On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> >> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >>
> >> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> >> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> >> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> >> platform.
> >>
> >> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >> ---
> >> This patch depends on:
> >> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> >> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> > 
> > If it is a fix for the patch which is still in flight, then stop posting
> > it as a separate patch. PLease work with the original series author to
> > get it squashed into the posted patch.
> The base changes are merged internally in QLI 2.0 already, it can't take additional changes. The base changes are PCIe specific, and this change is WLAN related.

What does QLI have to do with the upstream patches?

-- 
With best wishes
Dmitry

On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> 
> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> platform.

This didn't really improve.

> 
> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> ---
> This patch depends on:
> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> 
> Changes in v3:
> - Commit message changes, move Depends-on from commit message to
> cover-letter.
> - Introduce the PCIe architecture of RB3 Gen2 iindustrial mezzanine in
> the cover letter.

There is no cover letter. Also please read
Documentation/process/submitting-patches.rst and stop sending new
versions as replies to the old versions.

> - Link to v2: https://lore.kernel.org/all/20260311031145.2285056-1-hangtian.zhu@oss.qualcomm.com/
> 
> Changes in v2:
> - Commit message changes, change rb3gen2 to RB3 Gen2; wcn6750 to
> WCN6750; wpss to WPSS etc.
> - Link to v1: https://lore.kernel.org/all/20260311023219.2284643-1-hangtian.zhu@oss.qualcomm.com/
> ---
>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

-- 
With best wishes
Dmitry