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[PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS

Hangtian Zhu posted 1 patch 3 weeks, 6 days ago
There is a newer version of this series
.../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
1 file changed, 8 insertions(+)
[PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Hangtian Zhu 3 weeks, 6 days ago 
From: Hangtian Zhu <hangtian@oss.qualcomm.com>

Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
platform.

Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
---
 .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 2a2b7c2f9210..6594c7e1ea93 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -32,6 +32,10 @@ vreg_1p8: regulator-vreg-1p8 {
 	};
 };
 
+&remoteproc_wpss {
+       status = "disabled";
+};
+
 &spi11 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -280,3 +284,7 @@ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
 	};
 
 };
+
+&wifi {
+       status = "disabled";
+};
-- 
2.25.1
Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 6 days ago 
On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> 
> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial

You can't disable these devices on the mezzanine, they are not a part of
it.

> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie

PCIe0. How re they moved? What triggers the move?

> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> platform.
> 
> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

NAK. Don't invent non-standard tags.

> 
> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> ---
>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

-- 
With best wishes
Dmitry
Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Hangtian Zhu 3 weeks, 6 days ago 

On 3/11/2026 12:34, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>
>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> 
> You can't disable these devices on the mezzanine, they are not a part of
> it.
> 
>> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
> 
> PCIe0. How re they moved? What triggers the move?
Please refer to: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com/
On RB3 Gen2 industrial mezzanine, WCN6750 is not connected, instead TC9563 PCIe bridge is connected to PCIe0.

> 
>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
>> platform.
>>
>> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> 
> NAK. Don't invent non-standard tags.
> 
>>
>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
>> ---
>>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>
Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 5 days ago 
On Wed, Mar 11, 2026 at 03:06:08PM +0800, Hangtian Zhu wrote:
> 
> 
> On 3/11/2026 12:34, Dmitry Baryshkov wrote:
> > On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
> >> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >>
> >> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> > 
> > You can't disable these devices on the mezzanine, they are not a part of
> > it.
> > 
> >> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
> > 
> > PCIe0. How re they moved? What triggers the move?
> Please refer to: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com/
> On RB3 Gen2 industrial mezzanine, WCN6750 is not connected, instead TC9563 PCIe bridge is connected to PCIe0.

THis doesn't answer the question, what triggers the move? Is it done
automatically? Is there a pin that is sourced by the carrier board?
Is there something else?

> 
> > 
> >> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> >> platform.
> >>
> >> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> > 
> > NAK. Don't invent non-standard tags.
> > 
> >>
> >> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >> ---
> >>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
> >>  1 file changed, 8 insertions(+)
> >>
> > 
> 

-- 
With best wishes
Dmitry
Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Hangtian Zhu 3 weeks, 5 days ago 

On 3/12/2026 11:04, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 03:06:08PM +0800, Hangtian Zhu wrote:
>>
>>
>> On 3/11/2026 12:34, Dmitry Baryshkov wrote:
>>> On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
>>>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>>>
>>>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
>>>
>>> You can't disable these devices on the mezzanine, they are not a part of
>>> it.
>>>
>>>> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
>>>
>>> PCIe0. How re they moved? What triggers the move?
>> Please refer to: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com/
>> On RB3 Gen2 industrial mezzanine, WCN6750 is not connected, instead TC9563 PCIe bridge is connected to PCIe0.
> 
> THis doesn't answer the question, what triggers the move? Is it done
> automatically? Is there a pin that is sourced by the carrier board?
> Is there something else?
It's the hardware design itself. Industrial mezzanine (should be called 'kit') is not a plugin device on top of core kit, but a non‑modular integrated device.
Hardware redesigned QCS6490 SOM and disconnected WCN6750 from PCIe0 for this device, PCIe0 connects TC9563 PCIe bridge.

> 
>>
>>>
>>>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
>>>> platform.
>>>>
>>>> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
>>>
>>> NAK. Don't invent non-standard tags.
>>>
>>>>
>>>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>>> ---
>>>>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>>>>  1 file changed, 8 insertions(+)
>>>>
>>>
>>
>
Re: [PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 4 days ago 
On Thu, Mar 12, 2026 at 01:08:56PM +0800, Hangtian Zhu wrote:
> 
> 
> On 3/12/2026 11:04, Dmitry Baryshkov wrote:
> > On Wed, Mar 11, 2026 at 03:06:08PM +0800, Hangtian Zhu wrote:
> >>
> >>
> >> On 3/11/2026 12:34, Dmitry Baryshkov wrote:
> >>> On Wed, Mar 11, 2026 at 11:11:45AM +0800, Hangtian Zhu wrote:
> >>>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >>>>
> >>>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> >>>
> >>> You can't disable these devices on the mezzanine, they are not a part of
> >>> it.
> >>>
> >>>> mezzanine platform, pcie0 lines are moved from WCN6750 to QPS615 pcie
> >>>
> >>> PCIe0. How re they moved? What triggers the move?
> >> Please refer to: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com/
> >> On RB3 Gen2 industrial mezzanine, WCN6750 is not connected, instead TC9563 PCIe bridge is connected to PCIe0.
> > 
> > THis doesn't answer the question, what triggers the move? Is it done
> > automatically? Is there a pin that is sourced by the carrier board?
> > Is there something else?
> It's the hardware design itself. Industrial mezzanine (should be called 'kit') is not a plugin device on top of core kit, but a non‑modular integrated device.
> Hardware redesigned QCS6490 SOM and disconnected WCN6750 from PCIe0 for this device, PCIe0 connects TC9563 PCIe bridge.

This needs to be explained in the commit message. Mention that the
resistors on SoM are soldered differently and that it's not a separate
pluggable mezzanine.

And having this in mind, this _must_ be squashed into the original
Industrial Kit / Mezzanine submission, together with all the
explanations.


> 
> > 
> >>
> >>>
> >>>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> >>>> platform.
> >>>>
> >>>> Depends-on: https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> >>>
> >>> NAK. Don't invent non-standard tags.
> >>>
> >>>>
> >>>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >>>> ---
> >>>>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
> >>>>  1 file changed, 8 insertions(+)
> >>>>
> >>>
> >>
> > 
> 

-- 
With best wishes
Dmitry
[PATCH v3] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Hangtian Zhu 3 weeks, 6 days ago 
From: Hangtian Zhu <hangtian@oss.qualcomm.com>

Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
platform.

Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
---
This patch depends on:
[PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

Changes in v3:
- Commit message changes, move Depends-on from commit message to
cover-letter.
- Introduce the PCIe architecture of RB3 Gen2 iindustrial mezzanine in
the cover letter.
- Link to v2: https://lore.kernel.org/all/20260311031145.2285056-1-hangtian.zhu@oss.qualcomm.com/

Changes in v2:
- Commit message changes, change rb3gen2 to RB3 Gen2; wcn6750 to
WCN6750; wpss to WPSS etc.
- Link to v1: https://lore.kernel.org/all/20260311023219.2284643-1-hangtian.zhu@oss.qualcomm.com/
---
 .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 2a2b7c2f9210..6594c7e1ea93 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -32,6 +32,10 @@ vreg_1p8: regulator-vreg-1p8 {
 	};
 };
 
+&remoteproc_wpss {
+       status = "disabled";
+};
+
 &spi11 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -280,3 +284,7 @@ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
 	};
 
 };
+
+&wifi {
+       status = "disabled";
+};
-- 
2.25.1
Re: [PATCH v3] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 5 days ago 
On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> 
> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> platform.
> 
> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> ---
> This patch depends on:
> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/

If it is a fix for the patch which is still in flight, then stop posting
it as a separate patch. PLease work with the original series author to
get it squashed into the posted patch.

> 

-- 
With best wishes
Dmitry
Re: [PATCH v3] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Hangtian Zhu 3 weeks, 5 days ago 

On 3/12/2026 11:07, Dmitry Baryshkov wrote:
> On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
>> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
>>
>> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
>> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
>> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
>> platform.
>>
>> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
>> ---
>> This patch depends on:
>> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
>> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> 
> If it is a fix for the patch which is still in flight, then stop posting
> it as a separate patch. PLease work with the original series author to
> get it squashed into the posted patch.
The base changes are merged internally in QLI 2.0 already, it can't take additional changes. The base changes are PCIe specific, and this change is WLAN related.
> 
>>
>
Re: [PATCH v3] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 4 days ago 
On Thu, Mar 12, 2026 at 04:20:10PM +0800, Hangtian Zhu wrote:
> 
> 
> On 3/12/2026 11:07, Dmitry Baryshkov wrote:
> > On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> >> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >>
> >> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> >> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> >> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> >> platform.
> >>
> >> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> >> ---
> >> This patch depends on:
> >> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> >> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> > 
> > If it is a fix for the patch which is still in flight, then stop posting
> > it as a separate patch. PLease work with the original series author to
> > get it squashed into the posted patch.
> The base changes are merged internally in QLI 2.0 already, it can't take additional changes. The base changes are PCIe specific, and this change is WLAN related.

What does QLI have to do with the upstream patches?

-- 
With best wishes
Dmitry
Re: [PATCH v3] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: disable WCN6750 and WPSS
Posted by Dmitry Baryshkov 3 weeks, 5 days ago 
On Wed, Mar 11, 2026 at 03:04:08PM +0800, Hangtian Zhu wrote:
> From: Hangtian Zhu <hangtian@oss.qualcomm.com>
> 
> Disable WCN6750 and WPSS on industrial mezzanine. On RB3 Gen2 industrial
> mezzanine platform, PCIe0 lines are moved from WCN6750 to TC9563 pcie
> bridge. Hence disable WPSS and WCN6750 nodes for industrial mezzanine
> platform.

This didn't really improve.

> 
> Signed-off-by: Hangtian Zhu <hangtian@oss.qualcomm.com>
> ---
> This patch depends on:
> [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
> https://lore.kernel.org/all/20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com/
> 
> Changes in v3:
> - Commit message changes, move Depends-on from commit message to
> cover-letter.
> - Introduce the PCIe architecture of RB3 Gen2 iindustrial mezzanine in
> the cover letter.

There is no cover letter. Also please read
Documentation/process/submitting-patches.rst and stop sending new
versions as replies to the old versions.

> - Link to v2: https://lore.kernel.org/all/20260311031145.2285056-1-hangtian.zhu@oss.qualcomm.com/
> 
> Changes in v2:
> - Commit message changes, change rb3gen2 to RB3 Gen2; wcn6750 to
> WCN6750; wpss to WPSS etc.
> - Link to v1: https://lore.kernel.org/all/20260311023219.2284643-1-hangtian.zhu@oss.qualcomm.com/
> ---
>  .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso    | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

-- 
With best wishes
Dmitry

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