[PATCH 0/8] iommu/vt-d: Hitless PASID updates via entry_sync

Lu Baolu posted 8 patches 1 month ago
drivers/iommu/Kconfig               |  14 ++
drivers/iommu/intel/Kconfig         |   4 +-
drivers/iommu/Makefile              |   1 +
drivers/iommu/entry_sync.h          |  66 +++++++
drivers/iommu/entry_sync_template.h | 143 ++++++++++++++
drivers/iommu/intel/iommu.h         |   8 +-
drivers/iommu/intel/trace.h         | 107 ++++++++++
drivers/iommu/entry_sync.c          |  68 +++++++
drivers/iommu/intel/iommu.c         |  51 ++---
drivers/iommu/intel/nested.c        |  13 +-
drivers/iommu/intel/pasid.c         | 291 +++++++++++++++++++---------
drivers/iommu/intel/svm.c           |   5 +-
12 files changed, 620 insertions(+), 151 deletions(-)
create mode 100644 drivers/iommu/entry_sync.h
create mode 100644 drivers/iommu/entry_sync_template.h
create mode 100644 drivers/iommu/entry_sync.c
[PATCH 0/8] iommu/vt-d: Hitless PASID updates via entry_sync
Posted by Lu Baolu 1 month ago
This is a follow-up to recent discussions on the iommu community mailing
list [1] [2] regarding potential race conditions in table entry updates.
After addressing atomicity in context and PASID entry updates [3], this
series modernizes Intel IOMMU driver by introducing a "hitless" update
mechanism.

The core of this series lifts the synchronization logic originally found
in the ARM SMMUv3 driver into a generic IOMMU library (entry_sync) and
plumbs it into the Intel IOMMU driver.

Traditionally, updating a PASID table entry while the hardware is
performing DMA required a disruptive "clear-then-update" sequence. By
analyzing "used bits" and enforcing 128-bit atomicity via CMPXCHG16B,
this library allows the driver to transition between translation modes
hitlessly whenever possible.

[1] https://lore.kernel.org/linux-iommu/20251227175728.4358-1-dmaluka@chromium.org/
[2] https://lore.kernel.org/linux-iommu/20260107201800.2486137-1-skhawaja@google.com/
[3] https://lore.kernel.org/linux-iommu/20260120061816.2132558-1-baolu.lu@linux.intel.com/

This series is also available on github:
[4] https://github.com/LuBaolu/intel-iommu/commits/pasid-entry-sync-v1

Best regards,
baolu

Jason Gunthorpe (1):
  iommu: Lift and generalize the STE/CD update code from SMMUv3

Lu Baolu (7):
  iommu/vt-d: Add entry_sync support for PASID entry updates
  iommu/vt-d: Require CMPXCHG16B for PASID support
  iommu/vt-d: Add trace events for PASID entry sync updates
  iommu/vt-d: Use intel_pasid_write() for first-stage setup
  iommu/vt-d: Use intel_pasid_write() for second-stage setup
  iommu/vt-d: Use intel_pasid_write() for pass-through setup
  iommu/vt-d: Use intel_pasid_write() for nested setup

 drivers/iommu/Kconfig               |  14 ++
 drivers/iommu/intel/Kconfig         |   4 +-
 drivers/iommu/Makefile              |   1 +
 drivers/iommu/entry_sync.h          |  66 +++++++
 drivers/iommu/entry_sync_template.h | 143 ++++++++++++++
 drivers/iommu/intel/iommu.h         |   8 +-
 drivers/iommu/intel/trace.h         | 107 ++++++++++
 drivers/iommu/entry_sync.c          |  68 +++++++
 drivers/iommu/intel/iommu.c         |  51 ++---
 drivers/iommu/intel/nested.c        |  13 +-
 drivers/iommu/intel/pasid.c         | 291 +++++++++++++++++++---------
 drivers/iommu/intel/svm.c           |   5 +-
 12 files changed, 620 insertions(+), 151 deletions(-)
 create mode 100644 drivers/iommu/entry_sync.h
 create mode 100644 drivers/iommu/entry_sync_template.h
 create mode 100644 drivers/iommu/entry_sync.c

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2.43.0