Add CPUID and MSR bit definitions required to support Intel Directed
Package Thermal Interrupts.
A CPU requests directed package-level thermal interrupts by setting bit 25
in IA32_THERM_INTERRUPT. Hardware acknowledges by setting bit 25 in
IA32_PACKAGE_THERM_STATUS, indicating that only CPUs that opted in will
receive the interrupt. If no CPU in the package requests it, delivery
falls back to broadcast.
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index dbe104df339b..487bf9da0cef 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -364,6 +364,7 @@
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* "hwp_pkg_req" HWP Package Level Request */
#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
#define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */
+#define X86_FEATURE_DIRECTED_PKG_THRM_INTR (14*32+24) /* Intel Directed Package Thermal Interrupt */
/* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
#define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6673601246b3..aa1c652a9581 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -995,6 +995,7 @@
#define THERM_INT_HIGH_ENABLE (1 << 0)
#define THERM_INT_LOW_ENABLE (1 << 1)
#define THERM_INT_PLN_ENABLE (1 << 24)
+#define THERM_DIRECTED_INTR_ENABLE (1 << 25)
#define MSR_IA32_THERM_STATUS 0x0000019c
@@ -1024,6 +1025,7 @@
#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
+#define PACKAGE_THERM_STATUS_DIRECTED_INTR_ACK (1 << 25)
#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
--
2.43.0On Mon, Mar 09, 2026 at 03:19:24PM -0700, Ricardo Neri wrote:
> Add CPUID and MSR bit definitions required to support Intel Directed
> Package Thermal Interrupts.
>
> A CPU requests directed package-level thermal interrupts by setting bit 25
> in IA32_THERM_INTERRUPT. Hardware acknowledges by setting bit 25 in
> IA32_PACKAGE_THERM_STATUS, indicating that only CPUs that opted in will
> receive the interrupt. If no CPU in the package requests it, delivery
> falls back to broadcast.
>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/include/asm/msr-index.h | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index dbe104df339b..487bf9da0cef 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -364,6 +364,7 @@
> #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* "hwp_pkg_req" HWP Package Level Request */
> #define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
> #define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */
Leave a space here to denote there's a hole
> +#define X86_FEATURE_DIRECTED_PKG_THRM_INTR (14*32+24) /* Intel Directed Package Thermal Interrupt */
Also, can we agree on one naming and stick to it?
What you have there basically screams "OMG, I am trying to say *everything*
in that single define name but there's no room." :)
Also, the defines you have here are all a little bit different and good luck
matching what is what in a couple of months.
So, how about
#define X86_FEATURE_DPTI (14*32+24) /* Intel Directed Package Thermal Interrupt */
and the comment explains what the acronym is?
> /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
> #define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 6673601246b3..aa1c652a9581 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -995,6 +995,7 @@
> #define THERM_INT_HIGH_ENABLE (1 << 0)
> #define THERM_INT_LOW_ENABLE (1 << 1)
> #define THERM_INT_PLN_ENABLE (1 << 24)
> +#define THERM_DIRECTED_INTR_ENABLE (1 << 25)
And then you can do:
#define DPTI_ENABLE (1 << 25)
>
> #define MSR_IA32_THERM_STATUS 0x0000019c
>
> @@ -1024,6 +1025,7 @@
>
> #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
> #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
> +#define PACKAGE_THERM_STATUS_DIRECTED_INTR_ACK (1 << 25)
Ditto here:
DPTI_ACK
And you can always add comments explaining the acronym...
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Tue, Mar 10, 2026 at 10:35:30AM +0100, Borislav Petkov wrote: > On Mon, Mar 09, 2026 at 03:19:24PM -0700, Ricardo Neri wrote: > > Add CPUID and MSR bit definitions required to support Intel Directed > > Package Thermal Interrupts. > > > > A CPU requests directed package-level thermal interrupts by setting bit 25 > > in IA32_THERM_INTERRUPT. Hardware acknowledges by setting bit 25 in > > IA32_PACKAGE_THERM_STATUS, indicating that only CPUs that opted in will > > receive the interrupt. If no CPU in the package requests it, delivery > > falls back to broadcast. > > > > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > arch/x86/include/asm/msr-index.h | 2 ++ > > 2 files changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index dbe104df339b..487bf9da0cef 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -364,6 +364,7 @@ > > #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* "hwp_pkg_req" HWP Package Level Request */ > > #define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */ Thank you very much for your comments, Boris! > > #define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */ > > Leave a space here to denote there's a hole Sure. > > > +#define X86_FEATURE_DIRECTED_PKG_THRM_INTR (14*32+24) /* Intel Directed Package Thermal Interrupt */ > > Also, can we agree on one naming and stick to it? > > What you have there basically screams "OMG, I am trying to say *everything* > in that single define name but there's no room." :) Indeed, I had the feeling. > > Also, the defines you have here are all a little bit different and good luck > matching what is what in a couple of months. > > So, how about > > #define X86_FEATURE_DPTI (14*32+24) /* Intel Directed Package Thermal Interrupt */ > > and the comment explains what the acronym is? Sure, I will take your suggestion. > > > /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ > > #define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */ > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > > index 6673601246b3..aa1c652a9581 100644 > > --- a/arch/x86/include/asm/msr-index.h > > +++ b/arch/x86/include/asm/msr-index.h > > @@ -995,6 +995,7 @@ > > #define THERM_INT_HIGH_ENABLE (1 << 0) > > #define THERM_INT_LOW_ENABLE (1 << 1) > > #define THERM_INT_PLN_ENABLE (1 << 24) > > +#define THERM_DIRECTED_INTR_ENABLE (1 << 25) > > And then you can do: > > #define DPTI_ENABLE (1 << 25) Would it be OK to name it THERM_DPTI_ENABLE? It would be more consistent with the naming of the other bits. > > > > > #define MSR_IA32_THERM_STATUS 0x0000019c > > > > @@ -1024,6 +1025,7 @@ > > > > #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) > > #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) > > +#define PACKAGE_THERM_STATUS_DIRECTED_INTR_ACK (1 << 25) > > Ditto here: > > DPTI_ACK Same here, would it be OK to name it PACKAGE_THERM_DPTI_ACK for consistency with other bits' names? > > And you can always add comments explaining the acronym... Sure. Thanks and BR, Ricardo
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