Add RPMH clock support for the Fillmore SoC to allow enabling/disabling of
clocks.
Signed-off-by: Aelin Reidel <aelin@mainlining.org>
---
drivers/clk/qcom/clk-rpmh.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 547729b1a8ee01cf28c11ee8c4bd2f36d7536e6d..aeb83720d8fb07a2d5f413b746a24670a570ee63 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -940,6 +940,27 @@ static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
.num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
};
+static struct clk_hw *fillmore_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_fillmore = {
+ .clks = fillmore_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(fillmore_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -1029,6 +1050,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
+ { .compatible = "qcom,fillmore-rpmh-clk", .data = &clk_rpmh_fillmore},
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
--
2.53.0