From: Venkatesh Srinivas <venkateshs@chromium.org>

TCE augments the behavior of TLB invalidating instructions (INVLPG,
INVLPGB, and INVPCID) to only invalidate translations for relevant
intermediate mappings to the address range, rather than ALL intermdiate
translations.

The Linux kernel has been setting EFER.TCE if supported by the CPU since
commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
as it may improve performance.

KVM does not need to do anything to virtualize the feature, only
advertise it and allow setting EFER.TCE. If a TLB invalidating
instruction is not intercepted, it will behave according to the guest's
setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
KVM's emulation may invalidate more TLB entries, which is perfectly fine
as the CPU is allowed to invalidate more TLB entries that it strictly
needs to.

Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
EFER.TCE if available.

Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
Co-developed-by: Yosry Ahmed <yosry@kernel.org>
Signed-off-by: Yosry Ahmed <yosry@kernel.org>
---
 arch/x86/kvm/cpuid.c | 1 +
 arch/x86/kvm/x86.c   | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index fffbf087937d4..4f810f23b1d9b 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1112,6 +1112,7 @@ void kvm_initialize_cpu_caps(void)
 		F(XOP),
 		/* SKINIT, WDT, LWP */
 		F(FMA4),
+		F(TCE),
 		F(TBM),
 		F(TOPOEXT),
 		VENDOR_F(PERFCTR_CORE),
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 0b5d48e75b657..f12da9e92475e 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1743,6 +1743,9 @@ static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 	if (efer & EFER_NX && !guest_cpu_cap_has(vcpu, X86_FEATURE_NX))
 		return false;
 
+	if (efer & EFER_TCE && !guest_cpu_cap_has(vcpu, X86_FEATURE_TCE))
+		return false;
+
 	return true;
 
 }
@@ -10035,6 +10038,9 @@ static void kvm_setup_efer_caps(void)
 
 	if (kvm_cpu_cap_has(X86_FEATURE_AUTOIBRS))
 		kvm_enable_efer_bits(EFER_AUTOIBRS);
+
+	if (kvm_cpu_cap_has(X86_FEATURE_TCE))
+		kvm_enable_efer_bits(EFER_TCE);
 }
 
 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
-- 
2.53.0.473.g4a7958ca14-goog

> From: Venkatesh Srinivas <venkateshs@chromium.org>
>
> TCE augments the behavior of TLB invalidating instructions (INVLPG,
> INVLPGB, and INVPCID) to only invalidate translations for relevant
> intermediate mappings to the address range, rather than ALL intermdiate
> translations.
>
> The Linux kernel has been setting EFER.TCE if supported by the CPU since
> commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> as it may improve performance.
>
> KVM does not need to do anything to virtualize the feature, only
> advertise it and allow setting EFER.TCE. If a TLB invalidating
> instruction is not intercepted, it will behave according to the guest's
> setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
> KVM's emulation may invalidate more TLB entries, which is perfectly fine
> as the CPU is allowed to invalidate more TLB entries that it strictly
> needs to.
>
> Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
> EFER.TCE if available.
>
> Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
> Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> Signed-off-by: Yosry Ahmed <yosry@kernel.org>

I'll repeat what I said on that referenced patch.

What's the point?  AMD have said that TCE doesn't exist any more; it's a
bit that's no longer wired into anything.

You've got to get to pre-Zen hardware before this has any behavioural
effect, at which point the breath of testing is almost 0.

~Andrew

On Fri, Mar 6, 2026 at 5:54 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
>
> > From: Venkatesh Srinivas <venkateshs@chromium.org>
> >
> > TCE augments the behavior of TLB invalidating instructions (INVLPG,
> > INVLPGB, and INVPCID) to only invalidate translations for relevant
> > intermediate mappings to the address range, rather than ALL intermdiate
> > translations.
> >
> > The Linux kernel has been setting EFER.TCE if supported by the CPU since
> > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> > as it may improve performance.
> >
> > KVM does not need to do anything to virtualize the feature, only
> > advertise it and allow setting EFER.TCE. If a TLB invalidating
> > instruction is not intercepted, it will behave according to the guest's
> > setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
> > KVM's emulation may invalidate more TLB entries, which is perfectly fine
> > as the CPU is allowed to invalidate more TLB entries that it strictly
> > needs to.
> >
> > Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
> > EFER.TCE if available.
> >
> > Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
> > Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> > Signed-off-by: Yosry Ahmed <yosry@kernel.org>
>
> I'll repeat what I said on that referenced patch.
>
> What's the point?  AMD have said that TCE doesn't exist any more; it's a
> bit that's no longer wired into anything.
>
> You've got to get to pre-Zen hardware before this has any behavioural
> effect, at which point the breath of testing is almost 0.

Interesting, I missed that. Do you know where AMD said that?
(If so, why did we take 440a65b7d25f ("x86/mm: Enable AMD translation
cache extensions")?)

Thanks,
-- vs;

On Fri, Mar 6, 2026 at 5:54 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
>
> > From: Venkatesh Srinivas <venkateshs@chromium.org>
> >
> > TCE augments the behavior of TLB invalidating instructions (INVLPG,
> > INVLPGB, and INVPCID) to only invalidate translations for relevant
> > intermediate mappings to the address range, rather than ALL intermdiate
> > translations.
> >
> > The Linux kernel has been setting EFER.TCE if supported by the CPU since
> > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> > as it may improve performance.
> >
> > KVM does not need to do anything to virtualize the feature, only
> > advertise it and allow setting EFER.TCE. If a TLB invalidating
> > instruction is not intercepted, it will behave according to the guest's
> > setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
> > KVM's emulation may invalidate more TLB entries, which is perfectly fine
> > as the CPU is allowed to invalidate more TLB entries that it strictly
> > needs to.
> >
> > Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
> > EFER.TCE if available.
> >
> > Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
> > Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> > Signed-off-by: Yosry Ahmed <yosry@kernel.org>
>
> I'll repeat what I said on that referenced patch.
>
> What's the point?  AMD have said that TCE doesn't exist any more; it's a
> bit that's no longer wired into anything.
>
> You've got to get to pre-Zen hardware before this has any behavioural
> effect, at which point the breath of testing is almost 0.

Oh, I did not know that, thanks for pointing it out.

I'll leave it up to Sean whether to pick this up (because Linux guests
still set the bit), just pick up patches 1-2 as cleanups, or drop this
entirely.

On Mon, Mar 09, 2026, Yosry Ahmed wrote:
> On Fri, Mar 6, 2026 at 5:54 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
> >
> > > From: Venkatesh Srinivas <venkateshs@chromium.org>
> > >
> > > TCE augments the behavior of TLB invalidating instructions (INVLPG,
> > > INVLPGB, and INVPCID) to only invalidate translations for relevant
> > > intermediate mappings to the address range, rather than ALL intermdiate
> > > translations.
> > >
> > > The Linux kernel has been setting EFER.TCE if supported by the CPU since
> > > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> > > as it may improve performance.
> > >
> > > KVM does not need to do anything to virtualize the feature, only
> > > advertise it and allow setting EFER.TCE. If a TLB invalidating
> > > instruction is not intercepted, it will behave according to the guest's
> > > setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
> > > KVM's emulation may invalidate more TLB entries, which is perfectly fine
> > > as the CPU is allowed to invalidate more TLB entries that it strictly
> > > needs to.
> > >
> > > Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
> > > EFER.TCE if available.
> > >
> > > Signed-off-by: Venkatesh Srinivas <venkateshs@chromium.org>
> > > Co-developed-by: Yosry Ahmed <yosry@kernel.org>
> > > Signed-off-by: Yosry Ahmed <yosry@kernel.org>
> >
> > I'll repeat what I said on that referenced patch.
> >
> > What's the point?  AMD have said that TCE doesn't exist any more; it's a
> > bit that's no longer wired into anything.
> >
> > You've got to get to pre-Zen hardware before this has any behavioural
> > effect, at which point the breath of testing is almost 0.
> 
> Oh, I did not know that, thanks for pointing it out.
> 
> I'll leave it up to Sean whether to pick this up (because Linux guests
> still set the bit), just pick up patches 1-2 as cleanups, or drop this
> entirely.

I'll grab 1-2 and leave 3 alone, at least for now.  It _should_ do no harm, but
it would really suck to discover that pre-Zen hardware has a TLB bug that affects
TCE, or worse, affects TCE but only for ASID!=0 translations or something.

If new CPUs ever use TCE, it'll be trivial to enable at that time.

> > I'll leave it up to Sean whether to pick this up (because Linux guests
> > still set the bit), just pick up patches 1-2 as cleanups, or drop this
> > entirely.
>
> I'll grab 1-2 and leave 3 alone, at least for now.  It _should_ do no harm, but
> it would really suck to discover that pre-Zen hardware has a TLB bug that affects
> TCE, or worse, affects TCE but only for ASID!=0 translations or something.

Sounds good to me, thanks.