[v1] ASoC: codecs: cs42l84: set up PLL for more sample rates

[PATCH] ASoC: codecs: cs42l84: set up PLL for more sample rates

Posted by James Calligeros 1 month ago

Previously, this driver only advertised support for 48 kHz and
96 kHz sample rates, as there was no PLL configuration data
specified for any other sample rate/BCLK.

The CS42L84 is an Apple-specific variant of CS42L42. The PLL
configuration parameters for a variety of common BCLKs are
available in the latter's datasheet. What happens if we just
use those? As it turns out, they work just fine.

Fill out more PLL config parameters in the PLL config lookup
table, and advertise the corresponding sample rates to userspace.
This enables 44.1, 88.2, 176.4 and 192 kHz output and input.

Signed-off-by: James Calligeros <jcalligeros99@gmail.com>
---
 sound/soc/codecs/cs42l84.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/cs42l84.c b/sound/soc/codecs/cs42l84.c
index 1e1307a16f81..eba2c900b8e4 100644
--- a/sound/soc/codecs/cs42l84.c
+++ b/sound/soc/codecs/cs42l84.c
@@ -357,8 +357,11 @@ struct cs42l84_pll_params {
  * Common PLL Settings for given BCLK
  */
 static const struct cs42l84_pll_params pll_ratio_table[] = {
+	{  2822400, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
 	{  3072000, 1, 0, 0x40, 0x000000, 0x03, 0x10, 12288000},
+	{  5644800, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
 	{  6144000, 1, 1, 0x40, 0x000000, 0x03, 0x10, 12288000},
+	{ 11289600, 0, 0, 0, 0, 0, 0,                 11289600},
 	{ 12288000, 0, 0, 0, 0, 0, 0,                 12288000},
 	{ 24576000, 1, 3, 0x40, 0x000000, 0x03, 0x10, 12288000},
 };
@@ -670,14 +673,18 @@ static struct snd_soc_dai_driver cs42l84_dai = {
 			.stream_name = "Playback",
 			.channels_min = 1,
 			.channels_max = 2,
-			.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
+				SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
+				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
 			.formats = CS42L84_FORMATS,
 		},
 		.capture = {
 			.stream_name = "Capture",
 			.channels_min = 1,
 			.channels_max = 1,
-			.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
+				SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
+				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
 			.formats = CS42L84_FORMATS,
 		},
 		.symmetric_rate = 1,

---
base-commit: c40816209b5768d45aabb81f9c6ff8296ec58c32
change-id: 20260307-cs42l84-rates-c9e23e20209d

Best regards,
-- 
James Calligeros <jcalligeros99@gmail.com>

Re: [PATCH] ASoC: codecs: cs42l84: set up PLL for more sample rates

Posted by Mark Brown 4 weeks, 1 day ago

On Sat, Mar 07, 2026 at 10:44:18AM +1000, James Calligeros wrote:

> Fill out more PLL config parameters in the PLL config lookup
> table, and advertise the corresponding sample rates to userspace.
> This enables 44.1, 88.2, 176.4 and 192 kHz output and input.

>  static const struct cs42l84_pll_params pll_ratio_table[] = {
> +	{  2822400, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
>  	{  3072000, 1, 0, 0x40, 0x000000, 0x03, 0x10, 12288000},
> +	{  5644800, 1, 0, 0x40, 0x000000, 0x03, 0x10, 11289600},
>  	{  6144000, 1, 1, 0x40, 0x000000, 0x03, 0x10, 12288000},
> +	{ 11289600, 0, 0, 0, 0, 0, 0,                 11289600},
>  	{ 12288000, 0, 0, 0, 0, 0, 0,                 12288000},
>  	{ 24576000, 1, 3, 0x40, 0x000000, 0x03, 0x10, 12288000},
>  };

These are adding 44.1kHz based rates with a new value for MCLK (the
final value in each entry).  Those values are read with a switch
statement in cs42l84_pll_config but that only has an entry for 24.576MHz
for some reason, that won't match 112.896MHz and will just leave the
pll_mclk_f with whatever value it had before.  Don't we need a new case
statement there for the new MCLK?

Re: [PATCH] ASoC: codecs: cs42l84: set up PLL for more sample rates

Posted by James Calligeros 4 weeks, 1 day ago

Hi Mark,

On Wednesday, 11 March 2026 4:51:25 am Australian Eastern Standard Time Mark 
Brown wrote:
> These are adding 44.1kHz based rates with a new value for MCLK (the
> final value in each entry).  Those values are read with a switch
> statement in cs42l84_pll_config but that only has an entry for 24.576MHz
> for some reason, that won't match 112.896MHz and will just leave the
> pll_mclk_f with whatever value it had before.  Don't we need a new case
> statement there for the new MCLK?

Yes and no. According to the datasheet, the chip only requires the PLL to be
in the "region" of 12 or 24 MHz. Since we only have 12 MHz region PLL configs
in our table, this does actually work without changes, albeit unintutitively
(and accidentally).

On 42L42, this is configured using the MCLKDIV and MCLK_SRC_SEL bits, which
behave identically to what we've ended up calling MCLK_F. I will add an
explicit arm to the case statement and a comment explaining this so that it is
not ambiguous.

Regards,
James