[PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

Rob Herring (Arm) posted 1 patch 3 weeks, 6 days ago
arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
[PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes
Posted by Rob Herring (Arm) 3 weeks, 6 days ago
i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
temporary buffers. The SRAM is larger than 96KB, but that is all that is
available to non-secure world.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
v2:
 - Increase the APB freq to 133MHz
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 7b27012dfcb5..95cc60158349 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -43,6 +43,29 @@ map0 {
 			};
 		};
 	};
+
+	sram: sram@20480000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x20480000 0x0 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x20480000 0x18000>;
+	};
+
+	soc@0 {
+		npu@4a900000 {
+			compatible = "fsl,imx93-npu", "arm,ethos-u65";
+			reg = <0x4a900000 0x1000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&mlmix>;
+			clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+			assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			assigned-clock-rates = <800000000>, <133000000>;
+		};
+	};
 };
 
 &aips1 {
-- 
2.51.0
Re: [PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes
Posted by Frank Li 1 week, 3 days ago
On Fri, 06 Mar 2026 14:31:02 -0600, Rob Herring (Arm) wrote:
> i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
> temporary buffers. The SRAM is larger than 96KB, but that is all that is
> available to non-secure world.
>
>

Applied, thanks!

[1/1] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes
      commit: c95a5c0b55664ff938371b058673f294ce01fe1b

Move sram@20480000 node after soc@0 because keep order by address
Fix line assigned-clock-parents to keep below 100 char to avoid checkpatch
warning.

About sram size discussion, we can fix later.

Best regards,
--
Frank Li <Frank.Li@nxp.com>
Re: [PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes
Posted by Peter Robinson 3 weeks, 3 days ago
On Fri, 6 Mar 2026 at 20:31, Rob Herring (Arm) <robh@kernel.org> wrote:
>
> i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for
> temporary buffers. The SRAM is larger than 96KB, but that is all that is
> available to non-secure world.
>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> # Tested on a NXP
i.MX93 11X11 FRDM board

> ---
> v2:
>  - Increase the APB freq to 133MHz
> ---
>  arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index 7b27012dfcb5..95cc60158349 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -43,6 +43,29 @@ map0 {
>                         };
>                 };
>         };
> +
> +       sram: sram@20480000 {
> +               compatible = "mmio-sram";
> +               reg = <0x0 0x20480000 0x0 0x18000>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0x0 0x0 0x20480000 0x18000>;
> +       };
> +
> +       soc@0 {
> +               npu@4a900000 {
> +                       compatible = "fsl,imx93-npu", "arm,ethos-u65";
> +                       reg = <0x4a900000 0x1000>;
> +                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +                       power-domains = <&mlmix>;
> +                       clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
> +                       clock-names = "core", "apb";
> +                       sram = <&sram>;
> +                       assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
> +                       assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +                       assigned-clock-rates = <800000000>, <133000000>;
> +               };
> +       };
>  };
>
>  &aips1 {
> --
> 2.51.0
>