Add the bindings for Neutron, a Neural Processing Unit from NXP.
Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
v2:
- clock fixes: add description, rename, make clocks mandatory
- rename node from neutron to npu
- fix indentation
---
.../devicetree/bindings/npu/nxp,imx95-neutron.yaml | 96 ++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
new file mode 100644
index 000000000000..a06de4bc3f0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/npu/nxp,imx95-neutron.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Neutron NPU
+
+maintainers:
+ - Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
+ - Jiwei Fu <jiwei.fu@nxp.com>
+
+description:
+ Neutron is an NPU from NXP targeting edge AI inference applications.
+ Initially supported on i.MX95 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - nxp,imx95-neutron
+
+ reg:
+ items:
+ - description: Register space
+ - description: Instruction area of the TCM space
+ - description: Data area of the TCM space
+
+ reg-names:
+ items:
+ - const: regs
+ - const: itcm
+ - const: dtcm
+
+ memory-region:
+ description:
+ Phandle referencing a "shared-dma-pool" to be used for Neutron
+ inference buffers, which need to be 1MB aligned.
+
+ The memory region must be defined with alignment of 1MB and size
+ should be large enough to accommodate the targeted ML models. It
+ should be marked as reusable.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core clock
+ - description: APB bus clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: apb
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - memory-region
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ npu@4ab00000 {
+ compatible = "nxp,imx95-neutron";
+ reg = <0x0 0x4ab00000 0x0 0x00000400>,
+ <0x0 0x4AB10000 0x0 0x00010000>,
+ <0x0 0x4AB08000 0x0 0x00008000>;
+ reg-names = "regs", "itcm", "dtcm";
+ memory-region = <&neutron_pool>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 68>, <&scmi_clk 67>;
+ clock-names = "core", "apb";
+ power-domains = <&scmi_devpd 20>;
+ };
+ };
+...
--
2.34.1