From: Ed Tsai <ed.tsai@mediatek.com>

On some platforms, the VCC regulator has a slow ramp-up time. Add a
delay after enabling VCC to ensure voltage has fully stabilized before
we enable the clocks.

Signed-off-by: Ed Tsai <ed.tsai@mediatek.com>
---
 drivers/ufs/core/ufshcd.c | 12 ++++++++++++
 include/ufs/ufshcd.h      |  6 ++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 899e663fea6e..bea72e7c1d32 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -9942,11 +9942,13 @@ static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
 #ifdef CONFIG_PM
 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 {
+	bool vcc_on = false;
 	int ret = 0;
 
 	if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
 	    !hba->dev_info.is_lu_power_on_wp) {
 		ret = ufshcd_setup_vreg(hba, true);
+		vcc_on = true;
 	} else if (!ufshcd_is_ufs_dev_active(hba)) {
 		if (!ufshcd_is_link_active(hba)) {
 			ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
@@ -9957,6 +9959,7 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 				goto vccq_lpm;
 		}
 		ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
+		vcc_on = true;
 	}
 	goto out;
 
@@ -9965,6 +9968,15 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
 vcc_disable:
 	ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
 out:
+	/*
+	 * On platforms with a slow VCC ramp-up, a delay is needed after
+	 * turning on VCC to ensure the voltage is stable before the
+	 * reference clock is enabled.
+	 */
+	if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
+	    hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
+		usleep_range(1000, 1100);
+
 	return ret;
 }
 #endif /* CONFIG_PM */
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 8563b6648976..bf50078708b9 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -690,6 +690,12 @@ enum ufshcd_quirks {
 	 * because it causes link startup to become unreliable.
 	 */
 	UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE		= 1 << 26,
+
+	/*
+	 * On some platforms, the VCC regulator has a slow ramp-up time. Add a
+	 * delay after enable VCC to ensure it's stable.
+	 */
+	UFSHCD_QUIRK_VCC_ON_DELAY			= 1 << 27,
 };
 
 enum ufshcd_caps {
-- 
2.45.2

On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> On some platforms, the VCC regulator has a slow ramp-up time. Add a
> delay after enabling VCC to ensure voltage has fully stabilized before
> we enable the clocks.

Reviewed-by: Bart Van Assche <bvanassche@acm.org>

On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> +	/*
> +	 * On platforms with a slow VCC ramp-up, a delay is needed after
> +	 * turning on VCC to ensure the voltage is stable before the
> +	 * reference clock is enabled.
> +	 */
> +	if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
> +	    hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
> +		usleep_range(1000, 1100);

Since the value of the delay is platform-dependent, has it been
considered to introduce a new vendor operation (vop)?

Thanks,

Bart.

On Thu, 2026-03-05 at 06:24 -0600, Bart Van Assche wrote:
> On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
> > +     /*
> > +      * On platforms with a slow VCC ramp-up, a delay is needed
> > after
> > +      * turning on VCC to ensure the voltage is stable before the
> > +      * reference clock is enabled.
> > +      */
> > +     if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on
> > &&
> > +         hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
> > +             usleep_range(1000, 1100);
> 
> Since the value of the delay is platform-dependent, has it been
> considered to introduce a new vendor operation (vop)?
> 
> Thanks,
> 
> Bart.

A vop does feel a bit heavyweight for a simple sleep. How about we add
a new configurable variable, similar to the approach used for the VCC
off delay?

Best,

Ed Tsai

On 3/5/26 6:19 PM, Ed Tsai (蔡宗軒) wrote:
> On Thu, 2026-03-05 at 06:24 -0600, Bart Van Assche wrote:
>> On 3/5/26 2:29 AM, ed.tsai@mediatek.com wrote:
>>> +     /*
>>> +      * On platforms with a slow VCC ramp-up, a delay is needed
>>> after
>>> +      * turning on VCC to ensure the voltage is stable before the
>>> +      * reference clock is enabled.
>>> +      */
>>> +     if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on
>>> &&
>>> +         hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
>>> +             usleep_range(1000, 1100);
>>
>> Since the value of the delay is platform-dependent, has it been
>> considered to introduce a new vendor operation (vop)?
>
> A vop does feel a bit heavyweight for a simple sleep. How about we add
> a new configurable variable, similar to the approach used for the VCC
> off delay?

Let's postpone introducing such a configuration variable until there is
a real need for such a configuration variable.

Bart.