On 3/5/26 5:47 AM, Hongyang Zhao wrote:
> Add clock IDs for MCLK_1 through MCLK_4 and internal digital codec core
> clock to the PRM clock driver. These clocks are needed to provide MCLK
> to external codecs connected via MI2S.
This patch has already been submitted previously by Neil, Please pick
the patch from https://lkml.org/lkml/2025/10/6/828
--srini
>
> Signed-off-by: Hongyang Zhao <hongyang.zhao@thundersoft.com>
> ---
> sound/soc/qcom/qdsp6/q6prm-clocks.c | 5 +++++
> sound/soc/qcom/qdsp6/q6prm.h | 11 +++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
> index 4c574b48ab00..8c28d33b2a54 100644
> --- a/sound/soc/qcom/qdsp6/q6prm-clocks.c
> +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
> @@ -59,6 +59,11 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
> Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
> Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
> Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_1),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_2),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_3),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_4),
> + Q6PRM_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
> Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
> "LPASS_HW_MACRO"),
> Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
> diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
> index a988a32086fe..85e6df6bd39f 100644
> --- a/sound/soc/qcom/qdsp6/q6prm.h
> +++ b/sound/soc/qcom/qdsp6/q6prm.h
> @@ -52,6 +52,17 @@
> /* Clock ID for QUINARY MI2S OSR CLK */
> #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
>
> +/* Clock ID for MCLK1 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_1 0x300
> +/* Clock ID for MCLK2 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_2 0x301
> +/* Clock ID for MCLK3 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_3 0x302
> +/* Clock ID for MCLK4 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_4 0x304
> +/* Clock ID for Internal Digital Codec Core */
> +#define Q6PRM_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
> +
> #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
> #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
>
>